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authorMichael Pavone <pavone@retrodev.com>2019-01-27 05:55:08 -0800
committerMichael Pavone <pavone@retrodev.com>2019-01-27 05:55:08 -0800
commit581bdf0c2d873c8b20e1feecba5258b50db68445 (patch)
treec298d5630bb3ee3a9caef770d8e2d9990882bbb6
parentb802ec327873dd0bf3875efe13b178e10134b159 (diff)
Added adc instruction to CPU DSL
-rwxr-xr-xcpu_dsl.py20
1 files changed, 19 insertions, 1 deletions
diff --git a/cpu_dsl.py b/cpu_dsl.py
index faafbfe..6d56e52 100755
--- a/cpu_dsl.py
+++ b/cpu_dsl.py
@@ -385,13 +385,31 @@ def _sextCImpl(prog, params, rawParms):
else:
fmt = '\n\t{dst} = {src} & 0x8000 ? {src} | 0xFFFF0000 : {src};'
return fmt.format(src=params[1], dst=params[2])
-
+
+def _adcCImpl(prog, params, rawParams):
+ carryFlag = None
+ for flag in prog.flags.flagCalc:
+ if prog.flags.flagCalc[flag] == 'carry':
+ carryFlag = flag
+ if carryFlag is None:
+ raise Exception('adc requires a defined carry flag')
+ base = '\n\t{dst} = {a} + {b} + ('.format(dst = params[2], a = params[0], b = params[1])
+ carryStorage = prog.flags.getStorage(carryFlag)
+ if type(carryStorage) is tuple:
+ reg,bit = carryStorage
+ reg = prog.resolveReg(reg, None, (), False)
+ check = '({reg} & 1 << {bit})'.format(reg=reg, bit=bit)
+ else:
+ check = prog.resolveReg(carryStorage, None, (), False)
+ return base + check + ' ? 1 : 0);'
+
_opMap = {
'mov': Op(lambda val: val).cUnaryOperator(''),
'not': Op(lambda val: ~val).cUnaryOperator('~'),
'lnot': Op(lambda val: 0 if val else 1).cUnaryOperator('!'),
'neg': Op(lambda val: -val).cUnaryOperator('-'),
'add': Op(lambda a, b: a + b).cBinaryOperator('+'),
+ 'adc': Op().addImplementation('c', 2, _adcCImpl),
'sub': Op(lambda a, b: b - a).cBinaryOperator('-'),
'lsl': Op(lambda a, b: a << b).cBinaryOperator('<<'),
'lsr': Op(lambda a, b: a >> b).cBinaryOperator('>>'),