diff options
| author | Mike Pavone <pavone@retrodev.com> | 2013-01-05 02:18:31 -0800 |
|---|---|---|
| committer | Mike Pavone <pavone@retrodev.com> | 2013-01-05 02:18:31 -0800 |
| commit | 1d885dfef99deb7c7e308bc8c19eb37c15cbafb9 (patch) | |
| tree | 5883fdc5c484be638768a63188aab04268babb87 | |
| parent | aaa2d93b6bc5e6aa6b5e120fd08315242417a816 (diff) | |
Implement more movem modes src
| -rw-r--r-- | m68k_to_x86.c | 94 |
1 files changed, 94 insertions, 0 deletions
diff --git a/m68k_to_x86.c b/m68k_to_x86.c index 2f15a3a..a5a29df 100644 --- a/m68k_to_x86.c +++ b/m68k_to_x86.c @@ -1152,6 +1152,100 @@ uint8_t * translate_m68k_movem(uint8_t * dst, m68kinst * inst, x86_68k_options * dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); } break; + case MODE_AREG_DISPLACE: + early_cycles += BUS; + reg = SCRATCH2; + if (opts->aregs[inst->dst.params.regs.pri] >= 0) { + dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D); + } else { + dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH1, SZ_D); + } + dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH1, SZ_D); + break; + case MODE_AREG_INDEX_DISP8: + early_cycles += 6; + if (opts->aregs[inst->dst.params.regs.pri] >= 0) { + dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D); + } else { + dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH1, SZ_D); + } + sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7; + if (inst->dst.params.regs.sec & 1) { + if (inst->dst.params.regs.sec & 0x10) { + if (opts->aregs[sec_reg] >= 0) { + dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); + } else { + dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); + } + } else { + if (opts->dregs[sec_reg] >= 0) { + dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); + } else { + dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); + } + } + } else { + if (inst->dst.params.regs.sec & 0x10) { + if (opts->aregs[sec_reg] >= 0) { + dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); + } else { + dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); + } + } else { + if (opts->dregs[sec_reg] >= 0) { + dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); + } else { + dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); + } + } + dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); + } + if (inst->dst.params.regs.displacement) { + dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH1, SZ_D); + } + break; + case MODE_PC_DISPLACE: + early_cycles += BUS; + dst = mov_ir(dst, inst->dst.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D); + break; + case MODE_PC_INDEX_DISP8: + early_cycles += 6; + dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D); + sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7; + if (inst->dst.params.regs.sec & 1) { + if (inst->dst.params.regs.sec & 0x10) { + if (opts->aregs[sec_reg] >= 0) { + dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); + } else { + dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); + } + } else { + if (opts->dregs[sec_reg] >= 0) { + dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); + } else { + dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); + } + } + } else { + if (inst->dst.params.regs.sec & 0x10) { + if (opts->aregs[sec_reg] >= 0) { + dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); + } else { + dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); + } + } else { + if (opts->dregs[sec_reg] >= 0) { + dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); + } else { + dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); + } + } + dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); + } + if (inst->dst.params.regs.displacement) { + dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH1, SZ_D); + } + break; case MODE_ABSOLUTE: early_cycles += 4; case MODE_ABSOLUTE_SHORT: |