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author | Michael Pavone <pavone@retrodev.com> | 2017-03-17 08:05:55 -0700 |
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committer | Michael Pavone <pavone@retrodev.com> | 2017-03-17 08:05:55 -0700 |
commit | c56f74f0913bc7c2ab200dee194b1d3df5d93522 (patch) | |
tree | 365af4c2f437dda3a793f2e9a922883751618df2 | |
parent | 8d489e3e7b30198df876ea76743a65f5a028eb70 (diff) |
Minor fix to timing of "early" overflow case in divs when the dividend is negative
-rw-r--r-- | m68k_core_x86.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/m68k_core_x86.c b/m68k_core_x86.c index 4aa30a5..55f3a28 100644 --- a/m68k_core_x86.c +++ b/m68k_core_x86.c @@ -1736,8 +1736,8 @@ static uint32_t divs(uint32_t dividend, m68k_context *context, uint32_t divisor_ context->flags[FLAG_V] = 1; context->flags[FLAG_N] = 1; context->flags[FLAG_Z] = 0; - //TODO: FIXME - this cycle count probably changes based on whether the dividend is negative - context->current_cycle += 16 * context->options->gen.clock_divider; + cycles += 2; + context->current_cycle += cycles * context->options->gen.clock_divider; return orig_dividend; } uint16_t quotient = 0; |