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authorMichael Pavone <pavone@retrodev.com>2020-04-23 20:57:14 -0700
committerMichael Pavone <pavone@retrodev.com>2020-04-23 20:57:14 -0700
commite1c19ba01f5e8c62873a57755d9dcb51ce631394 (patch)
tree492f08da499d92a1501ff9c0fb19ea84c21e0c6c
parent41659d2dd35bd9ad39366899ee9581643e38d0d8 (diff)
Fix autogenerated temp variables in interrupt subroutine in CPU DSL
-rwxr-xr-xcpu_dsl.py6
1 files changed, 5 insertions, 1 deletions
diff --git a/cpu_dsl.py b/cpu_dsl.py
index d36b757..f58749c 100755
--- a/cpu_dsl.py
+++ b/cpu_dsl.py
@@ -1597,7 +1597,11 @@ class Program:
pieces.append('\n\t\tif (context->cycles >= context->sync_cycle) {')
self.meta = {}
self.temp = {}
- self.subroutines[self.interrupt].inline(self, [], pieces, otype, None)
+ intpieces = []
+ self.subroutines[self.interrupt].inline(self, [], intpieces, otype, None)
+ for size in self.temp:
+ pieces.append('\n\tuint{sz}_t gen_tmp{sz}__;'.format(sz=size))
+ pieces += intpieces
pieces.append('\n\t\t}')
self.meta = {}
self.temp = {}