diff options
| author | Michael Pavone <pavone@retrodev.com> | 2016-04-26 23:13:37 -0700 |
|---|---|---|
| committer | Michael Pavone <pavone@retrodev.com> | 2016-04-26 23:13:37 -0700 |
| commit | 8b7027061d5d79712f2bdd859f55923d571efb4f (patch) | |
| tree | b7d0e553d1fa1f450e21f64e561a2b74bc849530 /backend_x86.c | |
| parent | 042768acd31ac2a59049db55e31b647c2eb51818 (diff) | |
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Diffstat (limited to 'backend_x86.c')
| -rw-r--r-- | backend_x86.c | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/backend_x86.c b/backend_x86.c index 2892f83..0619dd7 100644 --- a/backend_x86.c +++ b/backend_x86.c @@ -51,18 +51,23 @@ code_ptr gen_mem_fun(cpu_options * opts, memmap_chunk const * memmap, uint32_t n code_info *code = &opts->code; code_ptr start = code->cur; check_cycles(opts); + uint8_t is_write = fun_type == WRITE_16 || fun_type == WRITE_8; + uint8_t adr_reg = is_write ? opts->scratch2 : opts->scratch1; + uint8_t size = (fun_type == READ_16 || fun_type == WRITE_16) ? SZ_W : SZ_B; + if (size != SZ_B && opts->align_error_mask) { + test_ir(code, opts->align_error_mask, adr_reg, SZ_D); + jcc(code, CC_NZ, is_write ? opts->handle_align_error_write : opts->handle_align_error_read); + } cycles(opts, opts->bus_cycles); if (after_inc) { *after_inc = code->cur; } - uint8_t is_write = fun_type == WRITE_16 || fun_type == WRITE_8; - uint8_t adr_reg = is_write ? opts->scratch2 : opts->scratch1; + if (opts->address_size == SZ_D && opts->address_mask != 0xFFFFFFFF) { and_ir(code, opts->address_mask, adr_reg, SZ_D); } code_ptr lb_jcc = NULL, ub_jcc = NULL; uint16_t access_flag = is_write ? MMAP_WRITE : MMAP_READ; - uint8_t size = (fun_type == READ_16 || fun_type == WRITE_16) ? SZ_W : SZ_B; uint32_t ram_flags_off = opts->ram_flags_off; for (uint32_t chunk = 0; chunk < num_chunks; chunk++) { |