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authorMike Pavone <pavone@retrodev.com>2013-09-01 12:11:28 -0700
committerMike Pavone <pavone@retrodev.com>2013-09-01 12:11:28 -0700
commit48e201cf39a18628e33d51a7fba1ee706af18ade (patch)
tree10dd3aef1c9bd6ff053e7c02304811f2f8197f98 /blastem.c
parentf09e868c52d367731accb654a3de3c95c5694519 (diff)
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Diffstat (limited to 'blastem.c')
-rw-r--r--blastem.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/blastem.c b/blastem.c
index a4afa0b..432e98b 100644
--- a/blastem.c
+++ b/blastem.c
@@ -219,7 +219,7 @@ m68k_context * sync_components(m68k_context * context, uint32_t address)
if (gen->ym->write_cycle != CYCLE_NEVER) {
gen->ym->write_cycle = gen->ym->write_cycle >= mclks_per_frame/MCLKS_PER_68K ? gen->ym->write_cycle - mclks_per_frame/MCLKS_PER_68K : 0;
}
- //printf("reached frame end | 68K Cycles: %d, MCLK Cycles: %d\n", context->current_cycle, mclks);
+ printf("reached frame end | 68K Cycles: %d, MCLK Cycles: %d\n", context->current_cycle, mclks);
vdp_run_context(v_context, mclks_per_frame);
if (!headless) {
@@ -284,6 +284,7 @@ m68k_context * vdp_port_write(uint32_t vdp_port, m68k_context * context, uint16_
vdp_run_dma_done(v_context, mclks_per_frame);
if (v_context->cycles >= mclks_per_frame) {
if (!headless) {
+ printf("reached frame end | 68K Cycles: %d, MCLK Cycles: %d\n", context->current_cycle, v_context->cycles);
wait_render_frame(v_context, frame_limit);
}
vdp_adjust_cycles(v_context, mclks_per_frame);
@@ -301,7 +302,7 @@ m68k_context * vdp_port_write(uint32_t vdp_port, m68k_context * context, uint16_
}
}
}
- context->current_cycle = v_context->cycles / MCLKS_PER_68K;
+ //context->current_cycle = v_context->cycles / MCLKS_PER_68K;
}
} else if(vdp_port < 8) {
blocked = vdp_control_port_write(v_context, value);
@@ -343,6 +344,7 @@ m68k_context * vdp_port_write(uint32_t vdp_port, m68k_context * context, uint16_
exit(1);
}
if (v_context->cycles != before_cycle) {
+ printf("68K paused for %d cycles at cycle %d\n", v_context->cycles / MCLKS_PER_68K - context->current_cycle, context->current_cycle);
context->current_cycle = v_context->cycles / MCLKS_PER_68K;
}
} else if (vdp_port < 0x18) {