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authorMichael Pavone <pavone@retrodev.com>2019-02-09 11:34:31 -0800
committerMichael Pavone <pavone@retrodev.com>2019-02-09 11:34:31 -0800
commitac523751c5942ee5e167b3dd5de2e1ef1e2af172 (patch)
tree310bc221e4727c96b1333446531a2eb4ecf6c7ed /cpu_dsl.py
parentfa418eee3639bd2c966dabafdc5d643934953a6f (diff)
Optimization to memory access in new Z80 core
Diffstat (limited to 'cpu_dsl.py')
-rwxr-xr-xcpu_dsl.py19
1 files changed, 13 insertions, 6 deletions
diff --git a/cpu_dsl.py b/cpu_dsl.py
index 0f95fda..7bce683 100755
--- a/cpu_dsl.py
+++ b/cpu_dsl.py
@@ -1032,8 +1032,8 @@ class Registers:
def addReg(self, name, size):
self.regs[name] = size
- def addPointer(self, name, size):
- self.pointers[name] = size
+ def addPointer(self, name, size, count):
+ self.pointers[name] = (size, count)
def addRegArray(self, name, size, regs):
self.regArrays[name] = (size, regs)
@@ -1070,12 +1070,15 @@ class Registers:
def processLine(self, parts):
if len(parts) == 3:
- self.addRegArray(parts[0], int(parts[1]), int(parts[2]))
+ if parts[1].startswith('ptr'):
+ self.addPointer(parts[0], parts[1][3:], int(parts[2]))
+ else:
+ self.addRegArray(parts[0], int(parts[1]), int(parts[2]))
elif len(parts) > 2:
self.addRegArray(parts[0], int(parts[1]), parts[2:])
else:
if parts[1].startswith('ptr'):
- self.addPointer(parts[0], parts[1][3:])
+ self.addPointer(parts[0], parts[1][3:], 1)
else:
self.addReg(parts[0], int(parts[1]))
return self
@@ -1084,13 +1087,17 @@ class Registers:
fieldList = []
for pointer in self.pointers:
stars = '*'
- ptype = self.pointers[pointer]
+ ptype, count = self.pointers[pointer]
while ptype.startswith('ptr'):
stars += '*'
ptype = ptype[3:]
if ptype.isdigit():
ptype = 'uint{sz}_t'.format(sz=ptype)
- hFile.write('\n\t{ptype} {stars}{nm};'.format(nm=pointer, ptype=ptype, stars=stars))
+ if count > 1:
+ arr = '[{n}]'.format(n=count)
+ else:
+ arr = ''
+ hFile.write('\n\t{ptype} {stars}{nm}{arr};'.format(nm=pointer, ptype=ptype, stars=stars, arr=arr))
for reg in self.regs:
if not self.isRegArrayMember(reg):
fieldList.append((self.regs[reg], 1, reg))