diff options
author | Michael Pavone <pavone@retrodev.com> | 2019-01-27 14:37:37 -0800 |
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committer | Michael Pavone <pavone@retrodev.com> | 2019-01-27 14:37:37 -0800 |
commit | cc50b0eb09a5115507661092727d803d3d7b58f8 (patch) | |
tree | b839ea1376f819820840621ae3d30921c042d5f9 /cpu_dsl.py | |
parent | 581bdf0c2d873c8b20e1feecba5258b50db68445 (diff) |
Implemented sbc instruction in CPU DSL
Diffstat (limited to 'cpu_dsl.py')
-rwxr-xr-x | cpu_dsl.py | 22 |
1 files changed, 16 insertions, 6 deletions
@@ -385,23 +385,32 @@ def _sextCImpl(prog, params, rawParms): else: fmt = '\n\t{dst} = {src} & 0x8000 ? {src} | 0xFFFF0000 : {src};' return fmt.format(src=params[1], dst=params[2]) - -def _adcCImpl(prog, params, rawParams): + +def _getCarryCheck(prog): carryFlag = None for flag in prog.flags.flagCalc: if prog.flags.flagCalc[flag] == 'carry': carryFlag = flag if carryFlag is None: raise Exception('adc requires a defined carry flag') - base = '\n\t{dst} = {a} + {b} + ('.format(dst = params[2], a = params[0], b = params[1]) carryStorage = prog.flags.getStorage(carryFlag) if type(carryStorage) is tuple: reg,bit = carryStorage reg = prog.resolveReg(reg, None, (), False) - check = '({reg} & 1 << {bit})'.format(reg=reg, bit=bit) + return '({reg} & 1 << {bit})'.format(reg=reg, bit=bit) else: - check = prog.resolveReg(carryStorage, None, (), False) - return base + check + ' ? 1 : 0);' + return prog.resolveReg(carryStorage, None, (), False) + +def _adcCImpl(prog, params, rawParams): + + return '\n\t{dst} = {a} + {b} + ({check} ? 1 : 0);'.format(dst = params[2], + a = params[0], b = params[1], check=_getCarryCheck(prog) + ) + +def _sbcCImpl(prog, params, rawParams): + return '\n\t{dst} = {a} - {b} - ({check} ? 1 : 0);'.format(dst = params[2], + a = params[0], b = params[1], check=_getCarryCheck(prog) + ) _opMap = { 'mov': Op(lambda val: val).cUnaryOperator(''), @@ -411,6 +420,7 @@ _opMap = { 'add': Op(lambda a, b: a + b).cBinaryOperator('+'), 'adc': Op().addImplementation('c', 2, _adcCImpl), 'sub': Op(lambda a, b: b - a).cBinaryOperator('-'), + 'sbc': Op().addImplementation('c', 2, _sbcCImpl), 'lsl': Op(lambda a, b: a << b).cBinaryOperator('<<'), 'lsr': Op(lambda a, b: a >> b).cBinaryOperator('>>'), 'asr': Op(lambda a, b: a >> b).addImplementation('c', 2, _asrCImpl), |