diff options
| author | Michael Pavone <pavone@retrodev.com> | 2015-10-21 23:31:17 -0700 |
|---|---|---|
| committer | Michael Pavone <pavone@retrodev.com> | 2015-10-21 23:31:17 -0700 |
| commit | bc7046c222aedfcdbdb59c9ced6baebee684b057 (patch) | |
| tree | ed22ad4f6e25bbb41a02f3bfbf6ca30ae9f435f4 /m68k_core_x86.c | |
| parent | 2774b6e5fd4fb0ee9bd1a14df29bff237d927d59 (diff) | |
Implemented nbcd
Diffstat (limited to 'm68k_core_x86.c')
| -rw-r--r-- | m68k_core_x86.c | 33 |
1 files changed, 22 insertions, 11 deletions
diff --git a/m68k_core_x86.c b/m68k_core_x86.c index 32f143b..bb3c702 100644 --- a/m68k_core_x86.c +++ b/m68k_core_x86.c @@ -1373,18 +1373,29 @@ void translate_m68k_invalid(m68k_options *opts, m68kinst *inst) void translate_m68k_abcd_sbcd(m68k_options *opts, m68kinst *inst, host_ea *src_op, host_ea *dst_op) { code_info *code = &opts->gen.code; - if (src_op->base != opts->gen.scratch2) { - if (src_op->mode == MODE_REG_DIRECT) { - mov_rr(code, src_op->base, opts->gen.scratch2, SZ_B); - } else { - mov_rdispr(code, src_op->base, src_op->disp, opts->gen.scratch2, SZ_B); + if (inst->op == M68K_NBCD) { + if (dst_op->base != opts->gen.scratch2) { + if (dst_op->mode == MODE_REG_DIRECT) { + mov_rr(code, dst_op->base, opts->gen.scratch2, SZ_B); + } else { + mov_rdispr(code, dst_op->base, dst_op->disp, opts->gen.scratch2, SZ_B); + } } - } - if (dst_op->base != opts->gen.scratch1) { - if (dst_op->mode == MODE_REG_DIRECT) { - mov_rr(code, dst_op->base, opts->gen.scratch1, SZ_B); - } else { - mov_rdispr(code, dst_op->base, dst_op->disp, opts->gen.scratch1, SZ_B); + xor_rr(code, opts->gen.scratch1, opts->gen.scratch1, SZ_B); + } else { + if (src_op->base != opts->gen.scratch2) { + if (src_op->mode == MODE_REG_DIRECT) { + mov_rr(code, src_op->base, opts->gen.scratch2, SZ_B); + } else { + mov_rdispr(code, src_op->base, src_op->disp, opts->gen.scratch2, SZ_B); + } + } + if (dst_op->base != opts->gen.scratch1) { + if (dst_op->mode == MODE_REG_DIRECT) { + mov_rr(code, dst_op->base, opts->gen.scratch1, SZ_B); + } else { + mov_rdispr(code, dst_op->base, dst_op->disp, opts->gen.scratch1, SZ_B); + } } } uint8_t other_reg; |