diff options
| author | Michael Pavone <pavone@retrodev.com> | 2016-07-29 09:14:32 -0700 |
|---|---|---|
| committer | Michael Pavone <pavone@retrodev.com> | 2016-07-29 09:14:32 -0700 |
| commit | dc952788cdd9e36c4078e48bf777de1995c462cb (patch) | |
| tree | 04077ab6c3e7c9a7124abf9907e25531e0f4f195 /z80_to_x86.c | |
| parent | 0d356eba0712aa40408184645f7bb31f3b05b79a (diff) | |
Implement undocumented flag bits for block LD instructions
Diffstat (limited to 'z80_to_x86.c')
| -rw-r--r-- | z80_to_x86.c | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/z80_to_x86.c b/z80_to_x86.c index e3e738e..b2d7393 100644 --- a/z80_to_x86.c +++ b/z80_to_x86.c @@ -561,7 +561,15 @@ void translate_z80inst(z80inst * inst, z80_context * context, uint16_t address, zreg_to_native(opts, Z80_HL, opts->gen.scratch1); call(code, opts->read_8); zreg_to_native(opts, Z80_DE, opts->gen.scratch2); + mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); call(code, opts->write_8); + mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_XY), opts->gen.scratch1, SZ_B); + add_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B); + mov_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); + and_ir(code, 0x8, opts->gen.scratch1, SZ_B); + shl_ir(code, 4, opts->gen.scratch2, SZ_B); + or_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); + mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); cycles(&opts->gen, 2); if (opts->regs[Z80_DE] >= 0) { add_ir(code, 1, opts->regs[Z80_DE], SZ_W); @@ -588,7 +596,15 @@ void translate_z80inst(z80inst * inst, z80_context * context, uint16_t address, zreg_to_native(opts, Z80_HL, opts->gen.scratch1); call(code, opts->read_8); zreg_to_native(opts, Z80_DE, opts->gen.scratch2); + mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); call(code, opts->write_8); + mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_XY), opts->gen.scratch1, SZ_B); + add_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B); + mov_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); + and_ir(code, 0x8, opts->gen.scratch1, SZ_B); + shl_ir(code, 4, opts->gen.scratch2, SZ_B); + or_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); + mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); if (opts->regs[Z80_DE] >= 0) { add_ir(code, 1, opts->regs[Z80_DE], SZ_W); } else { @@ -621,7 +637,15 @@ void translate_z80inst(z80inst * inst, z80_context * context, uint16_t address, zreg_to_native(opts, Z80_HL, opts->gen.scratch1); call(code, opts->read_8); zreg_to_native(opts, Z80_DE, opts->gen.scratch2); + mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); call(code, opts->write_8); + mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_XY), opts->gen.scratch1, SZ_B); + add_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B); + mov_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); + and_ir(code, 0x8, opts->gen.scratch1, SZ_B); + shl_ir(code, 4, opts->gen.scratch2, SZ_B); + or_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); + mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); cycles(&opts->gen, 2); if (opts->regs[Z80_DE] >= 0) { sub_ir(code, 1, opts->regs[Z80_DE], SZ_W); @@ -648,7 +672,15 @@ void translate_z80inst(z80inst * inst, z80_context * context, uint16_t address, zreg_to_native(opts, Z80_HL, opts->gen.scratch1); call(code, opts->read_8); zreg_to_native(opts, Z80_DE, opts->gen.scratch2); + mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); call(code, opts->write_8); + mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_XY), opts->gen.scratch1, SZ_B); + add_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B); + mov_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); + and_ir(code, 0x8, opts->gen.scratch1, SZ_B); + shl_ir(code, 4, opts->gen.scratch2, SZ_B); + or_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); + mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); if (opts->regs[Z80_DE] >= 0) { sub_ir(code, 1, opts->regs[Z80_DE], SZ_W); } else { |