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-rw-r--r--backend_x86.c3
-rw-r--r--m68k_core_x86.c2
2 files changed, 4 insertions, 1 deletions
diff --git a/backend_x86.c b/backend_x86.c
index addc34e..f2bb421 100644
--- a/backend_x86.c
+++ b/backend_x86.c
@@ -224,6 +224,9 @@ code_ptr gen_mem_fun(cpu_options * opts, memmap_chunk const * memmap, uint32_t n
}
code_ptr not_code = code->cur + 1;
jcc(code, CC_NC, code->cur + 2);
+ if (memmap[chunk].mask != opts->address_mask) {
+ or_ir(code, memmap[chunk].start, opts->scratch1, opts->address_size);
+ }
call(code, opts->save_context);
call_args(code, opts->handle_code_write, 2, opts->scratch2, opts->context_reg);
mov_rr(code, RAX, opts->context_reg, SZ_PTR);
diff --git a/m68k_core_x86.c b/m68k_core_x86.c
index 6ad305d..ad64cd1 100644
--- a/m68k_core_x86.c
+++ b/m68k_core_x86.c
@@ -2267,7 +2267,7 @@ m68k_context * m68k_handle_code_write(uint32_t address, m68k_context * context)
{
m68k_options * options = context->options;
//TODO: Modify gen_mem_fun so that it passes the raw address instead of the masked one, then remove the OR below
- uint32_t inst_start = get_instruction_start(options, context->native_code_map, address | 0xE00000);
+ uint32_t inst_start = get_instruction_start(options, context->native_code_map, address);
if (inst_start) {
code_info *code = &options->gen.code;
code_ptr dst = get_native_address(context->options, inst_start);