diff options
| -rwxr-xr-x | cpu_dsl.py | 44 | ||||
| -rw-r--r-- | svp.cpu | 49 |
2 files changed, 54 insertions, 39 deletions
@@ -114,6 +114,7 @@ class Instruction(Block): output = [] prog.meta = {} prog.currentScope = self + self.regValues = {} for var in self.locals: output.append('\n\tuint{sz}_t {name};'.format(sz=self.locals[var], name=var)) fieldVals,_ = self.getFieldVals(value) @@ -510,9 +511,9 @@ class Switch(ChildBlock): def generate(self, prog, parent, fieldVals, output, otype): oldScope = prog.currentScope prog.currentScope = self - self.regValues = self.parent.regValues param = prog.resolveParam(self.param, parent, fieldVals) if type(param) is int: + self.regValues = self.parent.regValues if param in self.cases: if self.case_locals[param]: output.append('\n\t{') @@ -533,6 +534,7 @@ class Switch(ChildBlock): output.append('\n\tswitch(' + param + ')') output.append('\n\t{') for case in self.cases: + self.regValues = dict(self.parent.regValues) output.append('\n\tcase {0}: '.format(case) + '{') for local in self.case_locals[case]: output.append('\n\tuint{0}_t {1};'.format(self.case_locals[case][local], local)) @@ -541,6 +543,7 @@ class Switch(ChildBlock): output.append('\n\tbreak;') output.append('\n\t}') if self.default: + self.regValues = dict(self.parent.regValues) output.append('\n\tdefault: {') for local in self.default_locals: output.append('\n\tuint{0}_t {1};'.format(self.default_locals[local], local)) @@ -585,7 +588,9 @@ class If(ChildBlock): self.elseBody = [] self.curBody = self.body self.locals = {} - self.regValues = parent.regValues + self.elseLocals = {} + self.curLocals = self.locals + self.regValues = None def addOp(self, op): if op.op in ('case', 'arg'): @@ -595,18 +600,39 @@ class If(ChildBlock): size = op.params[1] self.locals[name] = size elif op.op == 'else': + self.curLocals = self.elseLocals self.curBody = self.elseBody else: self.curBody.append(op) + def localSize(self, name): + return self.curLocals.get(name) + + def resolveLocal(self, name): + if name in self.locals: + return name + return None + + def _genTrueBody(self): + self.curLocals = self.locals + for op in self.body: + op.generate(prog, self, fieldVals, output, otype) + + def _genFalseBody(self): + self.curLocals = self.elseLocals + for op in self.body: + op.generate(prog, self, fieldVals, output, otype) + + def _genConstParam(self, param): + if param: + self._genTrueBody() + else: + self._genFalseBody() + def generate(self, prog, parent, fieldVals, output, otype): + self.regValues = parent.regValues try: - if prog.checkBool(self.cond): - for op in self.body: - op.generate(prog, self, fieldVals, output, otype) - else: - for op in self.elseBody: - op.generate(prog, self, fieldVals, output, otype) + self._genConstParam(prog.checkBool(self.cond)) except Exception: if self.cond in _ifCmpImpl[otype]: output.append(_ifCmpImpl[otype][self.cond](prog, parent, fieldVals, output)) @@ -627,7 +653,7 @@ class If(ChildBlock): for op in self.elseBody: op.generate(prog, self, fieldVals, output, otype) else: - output.append('\n\tif ({cond}) {'.format(cond=cond)) + output.append('\n\tif ({cond}) '.format(cond=cond) + '{') for op in self.body: op.generate(prog, self, fieldVals, output, otype) if self.elseBody: @@ -71,11 +71,8 @@ svp_ram_read #loop decremenet meta modestr - mov reg tmp - switch rpl - case 0 - sub 1 reg reg - - default + + if rpl lsl 1 rpl rpl sub 1 rpl rpl local mask 16 @@ -84,19 +81,16 @@ svp_ram_read sub 1 tmp tmp and rpl tmp tmp or rpl reg reg - - end + else + sub 1 reg reg + end case 3 #loop increment meta modestr + and 7 st rpl - switch rpl - case 0 - sub 1 reg reg - - default + if rpl mov reg tmp lsl 1 rpl rpl sub 1 rpl rpl @@ -106,8 +100,8 @@ svp_ram_read add 1 tmp tmp and rpl tmp tmp or rpl reg reg - - end + else + sub 1 reg reg end and 255 idx idx @@ -184,13 +178,14 @@ svp_check_cond default meta flag 0 end - switch fval - case 0 - lnot flag invert - meta istrue invert - default + if fval meta istrue flag + + else + lnot flag invert + meta istrue invert + end PPP0000000000000 alu_n1 @@ -282,10 +277,8 @@ PPP0000000001111 alu_al 1001000FCCCC0OOO cond_mod svp_check_cond F C - switch istrue - case 0 - - default + if istrue + switch O case 2 asr a 1 a @@ -303,6 +296,7 @@ PPP0000000001111 alu_al abs a a update_flags N end + end 000000000DDD0SSS ld_int_int dis "ld %s, %s" internal.D internal.S @@ -508,10 +502,8 @@ PPP0000000001111 alu_al 0100100FCCCC0000 call_cond svp_check_cond F C svp_op_fetch - switch istrue - case 0 - default + if istrue svp_push pc mov scratch1 pc end @@ -519,10 +511,7 @@ PPP0000000001111 alu_al 0100110FCCCC0000 bra_cond svp_check_cond F C svp_op_fetch - switch istrue - case 0 - - default + if istrue mov scratch1 pc end |