diff options
| -rwxr-xr-x | cpu_dsl.py | 2 | ||||
| -rw-r--r-- | m68k.cpu | 108 | ||||
| -rw-r--r-- | trans.c | 8 |
3 files changed, 116 insertions, 2 deletions
@@ -899,7 +899,7 @@ class NormalOp: else: param = parent.resolveLocal(param) or param if param in fieldVals: - param = fieldVals[index] + param = fieldVals[param] prog.meta[self.params[0]] = param elif self.op == 'dis': #TODO: Disassembler @@ -861,6 +861,114 @@ m68k_save_dst end m68k_save_dst Z m68k_prefetch + +1110CCC0ZZ001RRR lsri + invalid Z 3 + switch C + case 0 + meta shift 8 + default + meta shift C + end + lsr dregs.R shift dregs.R Z + update_flags XNZV0C + add shift shift shift + switch Z + case 2 + add 4 shift shift + default + add 2 shift shift + end + cycles shift + #TODO: should this happen before or after the majority of the shift? + m68k_prefetch + +1110CCC0ZZ101RRR lsr_dn + invalid Z 3 + local shift 8 + and dregs.C 63 shift + lsr dregs.R shift dregs.R Z + update_flags XNZV0C + add shift shift shift + switch Z + case 2 + add 4 shift shift + default + add 2 shift shift + end + cycles shift + #TODO: should this happen before or after the majority of the shift? + m68k_prefetch + +1110001011MMMRRR lsr_ea + invalid M 0 + invalid M 1 + invalid M 7 R 2 + invalid M 7 R 3 + invalid M 7 R 4 + invalid M 7 R 5 + invalid M 7 R 6 + invalid M 7 R 7 + + m68k_fetch_dst_ea M R 0 + lsr dst 1 dst + update_flags XNZV0C + m68k_save_dst 0 + m68k_prefetch + +1110CCC1ZZ001RRR lsli + invalid Z 3 + switch C + case 0 + meta shift 8 + default + meta shift C + end + lsl dregs.R shift dregs.R Z + update_flags XNZV0C + add shift shift shift + switch Z + case 2 + add 4 shift shift + default + add 2 shift shift + end + cycles shift + #TODO: should this happen before or after the majority of the shift? + m68k_prefetch + +1110CCC1ZZ101RRR lsl_dn + invalid Z 3 + local shift 8 + and dregs.C 63 shift + lsl dregs.R shift dregs.R Z + update_flags XNZV0C + add shift shift shift + switch Z + case 2 + add 4 shift shift + default + add 2 shift shift + end + cycles shift + #TODO: should this happen before or after the majority of the shift? + m68k_prefetch + +1110001111MMMRRR lsl_ea + invalid M 0 + invalid M 1 + invalid M 7 R 2 + invalid M 7 R 3 + invalid M 7 R 4 + invalid M 7 R 5 + invalid M 7 R 6 + invalid M 7 R 7 + + m68k_fetch_dst_ea M R 0 + lsl dst 1 dst + update_flags XNZV0C + m68k_save_dst 0 + m68k_prefetch 00ZZRRRMMMEEESSS move invalid Z 0 @@ -40,7 +40,11 @@ m68k_context * sync_components(m68k_context * context, uint32_t address) m68k_context *reset_handler(m68k_context *context) { m68k_print_regs(context); +#ifdef NEW_CORE + printf("cycles: %d\n", context->cycles); +#else printf("cycles: %d\n", context->current_cycle); +#endif exit(0); //unreachable return context; @@ -82,8 +86,10 @@ int main(int argc, char ** argv) m68k_context * context = init_68k_context(&opts, reset_handler); context->mem_pointers[0] = memmap[0].buffer; context->mem_pointers[1] = memmap[1].buffer; +#ifdef NEW_CORE + context->cycles = 40; +#else context->current_cycle = 40; -#ifndef NEW_CORE context->target_cycle = context->sync_cycle = 8000; #endif m68k_reset(context); |