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AgeCommit message (Collapse)Author
2013-01-01Do a sync when interrupt mask changes so we can recompute the next interrupt ↵Mike Pavone
cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
2013-01-01Make writes to control and data port block when DMA is in progressMike Pavone
2013-01-01Bail out of disassembly of a particular stream when we hit an invalid ↵Mike Pavone
instruction
2013-01-01Add hgignore fileMike Pavone
2012-12-31Implement most of the "X" instructionsMike Pavone
2012-12-31Implement m68k_modified_ret_addrMike Pavone
2012-12-31Comment out some debug printfsMike Pavone
2012-12-31Fix infinite loop bug in sprite renderingMike Pavone
2012-12-31Fix DMA fills to VRAMMike Pavone
2012-12-31Fix DMA in progress flag in VDP status registerMike Pavone
2012-12-31Fix label names in disassemblerMike Pavone
2012-12-31Properly support references to odd addresses in label generation in ↵Mike Pavone
disassembler. Add labels for start and interrupts.
2012-12-31Fix VDP readsMike Pavone
2012-12-30Implemented HV counterMike Pavone
2012-12-30Fix some bugs in decoding cmpMike Pavone
2012-12-30Fix 68K->VDP DMAMike Pavone
2012-12-30Improve disassemblerMike Pavone
2012-12-30Add support for pc indexed addressing mode to leaMike Pavone
2012-12-30Support more address modes for jmpMike Pavone
2012-12-30Fix bug that was causing DMA fills to lock up under certain circumstancesMike Pavone
2012-12-30Make version register return correct value for USAMike Pavone
2012-12-29Fix swapMike Pavone
2012-12-29Cleanup bit instructions and fix bug in translate_m68k_move that caused ↵Mike Pavone
incorrect results once translate_m68k_src was fixed
2012-12-29Fix crash when printing error message about modified return addressMike Pavone
2012-12-29Fix check in translate_m68k_src that deals with instructions for which both ↵Mike Pavone
operands are registers that are not mapped to a native x86-64 register
2012-12-29Fix encoding of movsx instruction when used with new (i.e. r9-r15) ↵Mike Pavone
registers. This fixes the indexed addressing modes when used with a word-wide index register
2012-12-29Some fixes for translating code in located in RAMMike Pavone
2012-12-29Implement the rest of the bit instructionsMike Pavone
2012-12-29Implemented ROL and RORMike Pavone
2012-12-29Fix logic for switching between USP and SSPMike Pavone
2012-12-28Fix decoding of CMPAMike Pavone
2012-12-28Fix return address pushed to stack for jsrMike Pavone
2012-12-28cycles should return dstMike Pavone
2012-12-28Fix call_r in gen_x86 so that it properly returns a pointer to the location ↵Mike Pavone
after the generated instruction
2012-12-28Implement pea (untested).Mike Pavone
2012-12-28Fix Z80 busreq logicMike Pavone
2012-12-28Allow jmp/jsr to follow pc-relative addresses in disassemblerMike Pavone
2012-12-28Defer the correct address for pc relative jsr/jmpMike Pavone
2012-12-28Implement scc (untested)Mike Pavone
2012-12-28Fix decoding of SccMike Pavone
2012-12-28Implement more address modes for jsrMike Pavone
2012-12-28COmment out fifo full debug printfMike Pavone
2012-12-28Fix horizontal mask values for scroll plane map address calculationMike Pavone
2012-12-28Fix areg indexed mode for move dstMike Pavone
2012-12-28Implement ORI to CCR/SRMike Pavone
2012-12-28Implemented move from SRMike Pavone
2012-12-27Use unsigned comparisons for address decoding, exit when we hit an unhandled ↵Mike Pavone
addressing mode for jmp
2012-12-27Don't pre-emptively translate code at interrupt vectors as some PD ROMs have ↵Mike Pavone
these pointing at junk. Need some kind of heuristic for detecting garbage if I'm going to translate them ahead of time by default.
2012-12-27allocate a new native code chunk when we run out of spaceMike Pavone
2012-12-27Some fixes to add/addx sub/subx decodingMike Pavone