| Age | Commit message (Expand) | Author |
|---|
| 2013-04-28 | Implement EX, EXX and RST in Z80 core | Mike Pavone |
| 2013-01-25 | Fix overflow flag on ASL | Mike Pavone |
| 2013-01-03 | Implement MULU/MULS and DIVU/DIVS | Mike Pavone |
| 2012-12-31 | Implement most of the "X" instructions | Mike Pavone |
| 2012-12-29 | Implement the rest of the bit instructions | Mike Pavone |
| 2012-12-28 | Implement scc (untested) | Mike Pavone |
| 2012-12-26 | Initial stab at interrupt support. Make native code offsets bigger so I don't... | Mike Pavone |
| 2012-12-22 | Add support for indexed modes as a source, some work on jmp and jsr with areg... | Mike Pavone |
| 2012-12-21 | Implement more instructions and address modes | Mike Pavone |
| 2012-12-19 | Add support for BTST instruction (untested), absolute addressing mode for ins... | Mike Pavone |
| 2012-12-15 | Implement shift instructions (asl, lsl, asr, lsr). Add flags to register prin... | Mike Pavone |
| 2012-12-12 | Add untested support for and, eor, or, swap, tst and nop instructions. Add ca... | Mike Pavone |
| 2012-12-04 | M68K to x86 translation works for a limited subset of instructions and addres... | Mike Pavone |
| 2012-11-27 | Make x86 generator generic with respect to operand size for immediate paramet... | Mike Pavone |
| 2012-11-27 | x86 code gen, initial work on translator | Mike Pavone |
