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path: root/m68k_core_x86.c
AgeCommit message (Collapse)Author
2020-06-10Fix cycle timing of a number of 68K instructionsMichael Pavone
2020-04-25Fix instruction timing for addq.w #i, (ay) in dynarecMichael Pavone
2019-04-07Get 64-bit builds working for Windows targetMichael Pavone
2018-05-18Fix cycle counts for BCD instructions, RESET, and MOVE from SRMichael Pavone
2018-05-17Fix instruction timing for a number of instructions with only a single operandMichael Pavone
2018-01-03Fix silly bug in STOP implementation that caused excessive CPU usageMichael Pavone
2017-09-13Push correct PC onto stack on divide by zero for pc-relative caseMichael Pavone
2017-09-13Preserve original address when retranslating instructions instead of ↵Michael Pavone
switching to the lowest alias
2017-09-06Properly clear trace mode on interrupt or other exception. Fix NBCD with ↵Michael Pavone
memory destination
2017-08-11Avoid generating an instruction that would require a REX prefix when a7 is ↵Michael Pavone
used as a byte-wide source operand in 32-bit builds. Fixes a fatal error in Dragon's Fury when entering the option menu in a 32-bit build
2017-05-26Avoid splitting m68k_check_cycles_int_latch code across memory chunks since ↵Michael Pavone
it expects a byte-sized jump offset. Avoid an unnecessary m68k_check_cycles_int_latch for register to register moves
2017-05-23Fix interrupt latency for move.l with memory destinationMichael Pavone
2017-05-19Fix to M68K interrupt latency for most instructions. Still needs some work ↵Michael Pavone
for RAW_IMPL instructions besides move
2017-04-26Fix timing for branch not taken case in the M68K BCC intructionMichael Pavone
2017-04-24Fix interaction between 68K debugger and instruction retranslation due to ↵Michael Pavone
self modifying code or bank switching
2017-03-28Fix exit trace mode edge case. Call do_sync if trace mode bit is changed in ↵Michael Pavone
eori sr
2017-03-28Implemented M68K trace mode. Some edge cases/SR update paths still need workMichael Pavone
2017-03-22Fix SBCD edge cases to pass Flamewing's test ROM. Could use some cleanup to ↵Michael Pavone
produce better code for the SBCD case, but produces correct results now
2017-03-17Minor fix to timing of "early" overflow case in divs when the dividend is ↵Michael Pavone
negative
2017-03-15Cycle accurate implementation of divsMichael Pavone
2017-03-09Fix undefined flags on overflow and divide by zero for divu based on ↵Michael Pavone
hardware test. Fix saving result of divu when destination is not stored in a host register
2017-03-09Forgot to update flags in the "good" case of the new divu codeMichael Pavone
2017-03-03Cycle accurate divu and undefined flags for overflow caseMichael Pavone
2017-02-23WIP support for XBAND mapper hardwareMichael Pavone
2017-02-12Fix timing for instructions using BINARY_IMPLMichael Pavone
2017-02-04Cycle accurate MULU/MULS emulationMichael Pavone
2017-01-24Inefficient fix for overlapping instruction problem that was causing issues ↵Michael Pavone
with Outrunners
2016-12-28Remove memory map assumptions from Z80 core and move a little bit of logic ↵Michael Pavone
to the generic backend.c so it can be shared between CPU cores
2016-12-19Mostly working changes to allow support for multiple emulated system types ↵Michael Pavone
in main blastem program
2016-11-05Get Jaguar video interrupt workingMichael Pavone
2016-10-06Remove hacky assumption about Genesis memory map in M68K coreMichael Pavone
2016-10-06Add support for specifying a reset handler in the M68K core. Adjust memory ↵Michael Pavone
map initialization to handle extra field. Improved handling of out of bounds execution.
2016-05-10Fix bug in 68K movep.l when the destination is a register mapped to a host ↵Michael Pavone
register
2016-04-30Fix 68K interrupt handling some more. Fatal Rewind is working again.Michael Pavone
2016-04-27Implement privelege violation exceptionsMichael Pavone
2016-04-27Implemented IR and undefined bits of info word for address error exception ↵Michael Pavone
frames
2016-04-26Initial stab at implementing address error exceptions. Need to fill in the ↵Michael Pavone
value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
2016-04-26Implement illegal instruction trapMichael Pavone
2016-04-24Fix interrupt latency from STOP instruction status reg changes. Fix modified ↵Michael Pavone
code patching when non-standard aliases are used. This fixes the demo MDEM's First
2016-04-24Half assed, prefetch based open bus value emulation. Gets BlastEm up to ↵Michael Pavone
119/122 in VDP FIFO Testing
2016-04-24Fix order of writes for move.l with a predec destinationMichael Pavone
2016-04-23Properly imlement btst with an immediate destination. Fixes a crash in NHL 95.Michael Pavone
2015-12-02Fix problem in 68K debugger caused by stack alignment changeMichael Pavone
2015-11-27Fix a few lingering stack alignment rework bugsMichael Pavone
2015-11-25Partially working change to do proper stack alignment rather than doing a ↵Michael Pavone
lame alignment check when calling a C compile dfunction. 68K core seems okay, but Z80 is busted.
2015-11-14Prevent the current interrupt number from being changed while interrupt is ↵Michael Pavone
being processed. This fixes a bug in Sonic 2 split screen that showed up when interrupt timing was adjusted
2015-11-13It is now possible to switch back and forth between the menu ROM and the gameMichael Pavone
2015-11-08Initial work for allowing loading a ROM from menuMichael Pavone
2015-11-01Update timing and order of steps in interrupt processing to match latest ↵Michael Pavone
measurements
2015-10-31Implement interrupt latency. Fixes Sesame Street: Counting Cafe and gives ↵Michael Pavone
accurate results in my test ROM