| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2012-12-16 | Add preliminary support for JMP | Mike Pavone | |
| 2012-12-16 | Implement CLR, minor refactor of register offset calculation in context struct | Mike Pavone | |
| 2012-12-15 | Implement shift instructions (asl, lsl, asr, lsr). Add flags to register ↵ | Mike Pavone | |
| printout. Fix minor bug in shift/rotate instruction decoding. | |||
| 2012-12-12 | Add untested support for and, eor, or, swap, tst and nop instructions. Add ↵ | Mike Pavone | |
| call to m68k_save_result for add and sub so that they will properly save results for memory destinations | |||
| 2012-12-12 | Add support for dbcc instruction | Mike Pavone | |
| 2012-12-04 | Initial support for M68k reset vector, rather than starting at an arbitrary ↵ | Mike Pavone | |
| address | |||
| 2012-12-04 | M68K to x86 translation works for a limited subset of instructions and ↵ | Mike Pavone | |
| addressing modes | |||
| 2012-11-27 | x86 code gen, initial work on translator | Mike Pavone | |
