| Age | Commit message (Expand) | Author |
|---|
| 2012-12-21 | Fix some bugs in movem with a register list destination | Mike Pavone |
| 2012-12-21 | Implement a couple of supervisor instructions | Mike Pavone |
| 2012-12-21 | Implement more instructions and address modes | Mike Pavone |
| 2012-12-20 | Make the translator bail out if it hits an instruction I haven't implemented yet | Mike Pavone |
| 2012-12-20 | Fix BTST | Mike Pavone |
| 2012-12-20 | Gamepad support | Mike Pavone |
| 2012-12-19 | Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causin... | Mike Pavone |
| 2012-12-19 | Add support for BTST instruction (untested), absolute addressing mode for ins... | Mike Pavone |
| 2012-12-18 | ecx was getting clobbered before the relevant temp value was used in some cas... | Mike Pavone |
| 2012-12-18 | Get Flavio's color bar demo kind of sort of working | Mike Pavone |
| 2012-12-16 | Add preliminary support for JMP | Mike Pavone |
| 2012-12-16 | Implement CLR, minor refactor of register offset calculation in context struct | Mike Pavone |
| 2012-12-15 | Implement shift instructions (asl, lsl, asr, lsr). Add flags to register prin... | Mike Pavone |
| 2012-12-12 | Add untested support for and, eor, or, swap, tst and nop instructions. Add ca... | Mike Pavone |
| 2012-12-12 | Add support for dbcc instruction | Mike Pavone |
| 2012-12-04 | Initial support for M68k reset vector, rather than starting at an arbitrary a... | Mike Pavone |
| 2012-12-04 | M68K to x86 translation works for a limited subset of instructions and addres... | Mike Pavone |
| 2012-11-27 | x86 code gen, initial work on translator | Mike Pavone |
