Age | Commit message (Collapse) | Author |
|
|
|
|
|
CRAM/VSRAM undefined bit results. Set number of bits actually saved in VSRAM to 11
|
|
|
|
|
|
and VSRAM bits can be implemented properly
|
|
stab at handling undefined bits of VSRAM and CRAM.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
visual observations of direct color DMA demos. Remove debug print statements.
|
|
|
|
completed if the FIFO is not empty
|
|
|
|
|
|
|
|
|
|
|
|
performance gain and to make it easier to use OpenGL for rendering
|
|
|
|
|
|
switching out of interlace mode.
|
|
|
|
|
|
|
|
with the cycle count getting out of sync with what I expect
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Print out the sprite list in stateview.
|
|
|
|
interrupts. Also added the VINT pending flag to status port.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
emulation so that direct color DMA demos work
|
|
|
|
|
|
|