Age | Commit message (Collapse) | Author |
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--HG--
branch : opengl
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address 0 for reads to VSRAM at >= 40
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DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
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CRAM/VSRAM undefined bit results. Set number of bits actually saved in VSRAM to 11
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and VSRAM bits can be implemented properly
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stab at handling undefined bits of VSRAM and CRAM.
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visual observations of direct color DMA demos. Remove debug print statements.
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completed if the FIFO is not empty
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performance gain and to make it easier to use OpenGL for rendering
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switching out of interlace mode.
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with the cycle count getting out of sync with what I expect
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Print out the sprite list in stateview.
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interrupts. Also added the VINT pending flag to status port.
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