blastem.git - Oxore's fork of "blastem" emulator for ROM hacking (C)

Age	Commit message (Collapse)	Author
2014-06-18	Fix most of the breakage caused by the vcounter/hcounter changes	Michael Pavone

2014-06-17	Partially working switch to having a vcounter and hslot counter in the ↵	Michael Pavone
	context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
2014-06-16	Fix a few values reported by the vr debugger command. Add DMA registers to ↵	Michael Pavone
	vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
2014-02-08	Initial GDB remote debugging support. Lacks some features, but breakpoints ↵	Mike Pavone
	and basic inspection of registers and memory work.
2014-01-06	The local clone on my laptop got messed up and some changes had not been ↵	Michael Pavone
	pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
2013-10-31	Small optimization for H40 mode	Mike Pavone

2013-10-29	Merge	Mike Pavone

2013-10-27	Basic OpenGL rendering is working	Mike Pavone
	--HG-- branch : opengl
2013-10-07	Initial implementation of sprite overflow and sprite collision status ↵	Mike Pavone
	register flags
2013-09-17	Set VBLANK flag in status register when display is disabled	Mike Pavone

2013-09-17	Implement HV counter latch	Mike Pavone

2013-09-17	Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM ↵	Mike Pavone
	address 0 for reads to VSRAM at >= 40
2013-09-17	Fix DMA fill so that it does not cause observable changes to the FIFO. Get ↵	Mike Pavone
	DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
2013-09-16	Partial fix for DMA copy	Mike Pavone

2013-09-15	Clear the low 2 bits of CD when a register is written to	Mike Pavone

2013-09-15	Don't allow register writes to regs above when in Mode 4	Mike Pavone

2013-09-15	Remove read pending stuff, that had been added in an attempt to fix ↵	Mike Pavone
	CRAM/VSRAM undefined bit results. Set number of bits actually saved in VSRAM to 11
2013-09-15	Implement undocumented 8-bit VRAM read	Mike Pavone

2013-09-15	Fix VSRAM reads	Mike Pavone

2013-09-15	Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM ↵	Mike Pavone
	and VSRAM bits can be implemented properly
2013-09-13	Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial ↵	Mike Pavone
	stab at handling undefined bits of VSRAM and CRAM.
2013-09-10	Added copyright notice to source files and added GPL license text in COPYING	Mike Pavone

2013-09-10	Fix timing of backdrop rendering when the display is turned off	Mike Pavone

2013-09-10	Merge	Mike Pavone

2013-09-10	Implement FIFO latency and improve DMA accuracy	Mike Pavone

2013-09-08	Revert change to VBLANK flag timing based on new direct color DMA test	Mike Pavone

2013-09-02	Fix per-column scrolling bug	Mike Pavone

2013-09-02	Adjust VBLANK flag and refresh timing to be in line with logic analyzer and ↵	Mike Pavone
	visual observations of direct color DMA demos. Remove debug print statements.
2013-09-01	Merge	Mike Pavone

2013-09-01	Fix bug that caused a DMA fill to start after another DMA operation ↵	Mike Pavone
	completed if the FIFO is not empty
2013-07-26	Added support for saving savestates. Added gst savestate format test harness	Mike Pavone

2013-07-16	Add address/cd registers to VDP debug message	Mike Pavone

2013-07-15	Restore one of the VDP debugging modes	Mike Pavone

2013-07-12	Implement the scroll ring buffer properly without memcpy	Mike Pavone

2013-06-30	Refactor duplicated CRAM writing code and fix a bug in the process	Mike Pavone

2013-06-30	Make VDP render in native pixel format of the renderer for a modest ↵	Mike Pavone
	performance gain and to make it easier to use OpenGL for rendering
2013-06-29	Add support for loading GST format savestates	Mike Pavone

2013-06-23	Fix window layer in double res interlace mode	Mike Pavone

2013-06-23	Fix sprite y mask in interlace mode. Fix framebuffer selection when ↵	Mike Pavone
	switching out of interlace mode.
2013-06-23	Fix vscroll calculation in double resultion interlace mode	Mike Pavone

2013-06-22	Initial work on interlace	Mike Pavone

2013-05-15	Fix background color regsiter number	Mike Pavone

2013-05-14	Only latch video mode at the very beginning of the frame to avoid problems ↵	Mike Pavone
	with the cycle count getting out of sync with what I expect
2013-05-14	Update Z80 vint timing	Mike Pavone

2013-05-14	Update hv counter calculation for clock wonkiness	Mike Pavone

2013-05-14	Fixup VINT cycle and HBLANK flag for the previous timing fixes	Mike Pavone

2013-05-13	Initial stab at implementing funky clock adjustments during HSYNC for H40 mode	Mike Pavone

2013-05-13	Implement first line/last line weirdness in VDP	Mike Pavone

2013-05-13	Fewer magic numbers in the VDP core for the win	Mike Pavone

2013-05-13	Added some basic VDP debugging features to debugger. Fixed DMA enable bug	Mike Pavone