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2015-05-22Fix bug in vdp_next_hint that was causing HINTs to fire repeatedly when they ↵Michael Pavone
should not have fired at all based on an HINT interval that was larger than the number of active lines in the display
2015-05-21Restore the other 2 debug display modesMichael Pavone
2015-05-20Add some tests for hint timing and fix it properly this time.Michael Pavone
2015-05-20Upgrade to SDL 2.0 and drop support for the non-OpenGL render pathMichael Pavone
2015-05-20Update vscroll latch implementation to be more in line with what Eke-Eke has ↵Michael Pavone
observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
2015-05-19Small correction to VBLANK flag timing. Fixed some inconsistencies in ↵Michael Pavone
interrupt timing calculation.
2015-05-17Fix VDP status register PAL bit based on observations of the Titan Overdrive ↵Michael Pavone
demo
2015-05-16Adjust H32 vint slot in response to latest test ROM dataMichael Pavone
2015-05-16First pass at emulating a vscroll latch. Titan's Overdrive demo seems to ↵Michael Pavone
depend on the scroll value being latched early in the line before the HINT gets a chance to change it
2015-05-14Small horizontal interrupt fixesMichael Pavone
2015-05-13Add description of cd register value to vr debugger commandMichael Pavone
2015-05-11Fix frame counter increment and VINT cycle time calculationMichael Pavone
2015-05-11Sync fixes and logging to fix more sync issuesMichael Pavone
2015-01-04Some small synchronization improvements that do not seem to fix anythingMichael Pavone
2015-01-04Adjusted h40_hsync_cycles so that lines actually take 3420 mclks. Fixed ↵Michael Pavone
vdp_cycles_next_line to take h40_sync_cycles into account
2014-12-14Fix the HV counter and adjust the slots of certain VDP eventsMichael Pavone
2014-08-14Small fix to display of DMA source address in vr debug commandMichael Pavone
2014-06-18Remove debug printf that escaped into my previous commitMichael Pavone
2014-06-18Fix most of the breakage caused by the vcounter/hcounter changesMichael Pavone
2014-06-17Partially working switch to having a vcounter and hslot counter in the ↵Michael Pavone
context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
2014-06-16Fix a few values reported by the vr debugger command. Add DMA registers to ↵Michael Pavone
vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
2014-02-08Initial GDB remote debugging support. Lacks some features, but breakpoints ↵Mike Pavone
and basic inspection of registers and memory work.
2014-01-06The local clone on my laptop got messed up and some changes had not been ↵Michael Pavone
pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
2013-10-31Small optimization for H40 modeMike Pavone
2013-10-29MergeMike Pavone
2013-10-27Basic OpenGL rendering is workingMike Pavone
--HG-- branch : opengl
2013-10-07Initial implementation of sprite overflow and sprite collision status ↵Mike Pavone
register flags
2013-09-17Set VBLANK flag in status register when display is disabledMike Pavone
2013-09-17Implement HV counter latchMike Pavone
2013-09-17Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM ↵Mike Pavone
address 0 for reads to VSRAM at >= 40
2013-09-17Fix DMA fill so that it does not cause observable changes to the FIFO. Get ↵Mike Pavone
DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
2013-09-16Partial fix for DMA copyMike Pavone
2013-09-15Clear the low 2 bits of CD when a register is written toMike Pavone
2013-09-15Don't allow register writes to regs above when in Mode 4Mike Pavone
2013-09-15Remove read pending stuff, that had been added in an attempt to fix ↵Mike Pavone
CRAM/VSRAM undefined bit results. Set number of bits actually saved in VSRAM to 11
2013-09-15Implement undocumented 8-bit VRAM readMike Pavone
2013-09-15Fix VSRAM readsMike Pavone
2013-09-15Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM ↵Mike Pavone
and VSRAM bits can be implemented properly
2013-09-13Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial ↵Mike Pavone
stab at handling undefined bits of VSRAM and CRAM.
2013-09-10Added copyright notice to source files and added GPL license text in COPYINGMike Pavone
2013-09-10Fix timing of backdrop rendering when the display is turned offMike Pavone
2013-09-10MergeMike Pavone
2013-09-10Implement FIFO latency and improve DMA accuracyMike Pavone
2013-09-08Revert change to VBLANK flag timing based on new direct color DMA testMike Pavone
2013-09-02Fix per-column scrolling bugMike Pavone
2013-09-02Adjust VBLANK flag and refresh timing to be in line with logic analyzer and ↵Mike Pavone
visual observations of direct color DMA demos. Remove debug print statements.
2013-09-01MergeMike Pavone
2013-09-01Fix bug that caused a DMA fill to start after another DMA operation ↵Mike Pavone
completed if the FIFO is not empty
2013-07-26Added support for saving savestates. Added gst savestate format test harnessMike Pavone
2013-07-16Add address/cd registers to VDP debug messageMike Pavone
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