Age | Commit message (Collapse) | Author |
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interrupt timing calculation.
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depend on the scroll value being latched early in the line before the HINT gets a chance to change it
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context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
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register flags
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DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
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and VSRAM bits can be implemented properly
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stab at handling undefined bits of VSRAM and CRAM.
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performance gain and to make it easier to use OpenGL for rendering
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Print out the sprite list in stateview.
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interrupts. Also added the VINT pending flag to status port.
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cycle count got reset at end of frame.
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