From 1f7eb1afff1a9b13cde11a786145ba313df3334a Mon Sep 17 00:00:00 2001 From: Michael Pavone Date: Sat, 2 Feb 2019 23:02:19 -0800 Subject: Implemented LDI in new Z80 core --- cpu_dsl.py | 12 ++++++++++-- z80.cpu | 44 +++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 53 insertions(+), 3 deletions(-) diff --git a/cpu_dsl.py b/cpu_dsl.py index b38a83b..c3f1f70 100755 --- a/cpu_dsl.py +++ b/cpu_dsl.py @@ -873,11 +873,19 @@ def _geuCImpl(prog, parent, fieldVals, output): params = [prog.resolveParam(p, parent, fieldVals) for p in prog.lastOp.params] return '\n\tif ({a} >= {b}) '.format(a=params[1], b = params[0]) + '{' else: - raise ion(">=U not implemented in the general case yet") + raise Exception(">=U not implemented in the general case yet") + +def _eqCImpl(prog, parent, fieldVals, output): + return '\n\tif (!{a}) {'.format(a=prog.resolveParam(prog.lastDst, None, {})) + +def _neqCImpl(prog, parent, fieldVals, output): + return '\n\tif ({a}) {'.format(a=prog.resolveParam(prog.lastDst, None, {})) _ifCmpImpl = { 'c': { - '>=U': _geuCImpl + '>=U': _geuCImpl, + '=': _eqCImpl, + '!=': _neqCImpl } } #represents a DSL conditional construct diff --git a/z80.cpu b/z80.cpu index 1db3630..4a615fa 100644 --- a/z80.cpu +++ b/z80.cpu @@ -2015,4 +2015,46 @@ fdcb 11BBB110 set_iyd z80_set_index B tmp fdcb 11BBBRRR set_iyd_reg - z80_set_index B main.R \ No newline at end of file + z80_set_index B main.R + +ed 10100000 ldi + local tmp 16 + local tmp8 8 + lsl h 8 tmp + or l tmp tmp + mov tmp scratch1 + add 1 tmp tmp + mov tmp l + lsr tmp 8 h + ocall read_8 + cycles 1 + + add a scratch1 tmp8 + update_flags H0XN0 + + and 0x2 tmp8 tmp8 + lsl 4 tmp8 tmp8 + and 0x88 last_flag_result last_flag_result + or tmp8 last_flag_result last_flag_result + + lsl d 8 tmp + or e tmp tmp + mov tmp scratch2 + add 1 tmp tmp + mov tmp e + lsr tmp 8 d + ocall write_8 + + lsl b 8 tmp + or c tmp tmp + sub 1 tmp tmp + + mov tmp c + lsr tmp 8 b + mov c pvflag + or b pvflag pvflag + + + + cycles 5 + \ No newline at end of file -- cgit v1.2.3