From 53015149f581d73e44a75bb5322f8f803411a04e Mon Sep 17 00:00:00 2001
From: Michael Pavone <pavone@retrodev.com>
Date: Sat, 2 Feb 2019 15:35:15 -0800
Subject: Implemented RES instruction in new Z80 core

---
 cpu_dsl.py |  7 +++++++
 z80.cpu    | 43 ++++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 49 insertions(+), 1 deletion(-)

diff --git a/cpu_dsl.py b/cpu_dsl.py
index 58b84b4..b38a83b 100755
--- a/cpu_dsl.py
+++ b/cpu_dsl.py
@@ -745,6 +745,13 @@ class NormalOp:
 					output.append(_opMap['mov'].generate(otype, prog, shortProc, shortParams, None))
 			else:
 				output.append(opDef.generate(otype, prog, procParams, self.params, flagUpdates))
+				for dstIdx in opDef.outOp:
+					dst = self.params[dstIdx]
+					while dst in prog.meta:
+						dst = prog.meta[dst]
+					if dst in parent.regValues:
+						del parent.regValues[dst]
+					
 		elif self.op in prog.subroutines:
 			procParams = []
 			for param in self.params:
diff --git a/z80.cpu b/z80.cpu
index 57d3b2d..7a6b14c 100644
--- a/z80.cpu
+++ b/z80.cpu
@@ -1750,4 +1750,45 @@ fdcb 01BBBRRR bit_iyd
 	lsl 1 B tmp
 	lsr wz 8 last_flag_result
 	and scratch1 tmp tmp
-	update_flags SZH1PN0
\ No newline at end of file
+	update_flags SZH1PN0
+	
+cb 10BBBRRR res_reg
+	local tmp 8
+	lsl 1 B tmp
+	not tmp tmp
+	and main.R tmp main.R
+	
+cb 10BBB110 res_hl
+	z80_fetch_hl
+	cycles 1
+	local tmp 8
+	lsl 1 B tmp
+	not tmp tmp
+	and scratch1 tmp scratch1
+	z80_store_hl
+	
+z80_res_index
+	arg bit 8
+	arg tmp 8
+	lsl 1 bit tmp
+	not tmp tmp
+	mov wz scratch1
+	ocall read_8
+	cycles 1
+	and scratch1 tmp tmp
+	mov tmp scratch1
+	z80_store_index
+	
+ddcb 10BBB110 res_ixd
+	local tmp 8
+	z80_res_index B tmp
+	
+ddcb 10BBBRRR res_ixd_reg
+	z80_res_index B main.R
+	
+fdcb 10BBB110 res_iyd
+	local tmp 8
+	z80_res_index B tmp
+	
+fdcb 10BBBRRR res_iyd_reg
+	z80_res_index B main.R
\ No newline at end of file
-- 
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