From 4fc2cd522e1487ba69cdfc2c40c54f2c0ca51797 Mon Sep 17 00:00:00 2001 From: Michael Pavone Date: Wed, 27 Jul 2016 22:46:22 -0700 Subject: Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. --- backend_x86.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) (limited to 'backend_x86.c') diff --git a/backend_x86.c b/backend_x86.c index 0619dd7..2c9f083 100644 --- a/backend_x86.c +++ b/backend_x86.c @@ -3,15 +3,23 @@ void cycles(cpu_options *opts, uint32_t num) { - add_ir(&opts->code, num*opts->clock_divider, opts->cycles, SZ_D); + if (opts->limit < 0) { + sub_ir(&opts->code, num*opts->clock_divider, opts->cycles, SZ_D); + } else { + add_ir(&opts->code, num*opts->clock_divider, opts->cycles, SZ_D); + } } void check_cycles_int(cpu_options *opts, uint32_t address) { code_info *code = &opts->code; - cmp_rr(code, opts->cycles, opts->limit, SZ_D); + if (opts->limit < 0) { + or_rr(code, opts->cycles, opts->cycles, SZ_D); + } else { + cmp_rr(code, opts->cycles, opts->limit, SZ_D); + } code_ptr jmp_off = code->cur+1; - jcc(code, CC_A, jmp_off+1); + jcc(code, CC_NS, jmp_off+1); mov_ir(code, address, opts->scratch1, SZ_D); call(code, opts->handle_cycle_limit_int); *jmp_off = code->cur - (jmp_off+1); @@ -20,10 +28,14 @@ void check_cycles_int(cpu_options *opts, uint32_t address) void check_cycles(cpu_options * opts) { code_info *code = &opts->code; - cmp_rr(code, opts->cycles, opts->limit, SZ_D); + if (opts->limit < 0) { + or_rr(code, opts->cycles, opts->cycles, SZ_D); + } else { + cmp_rr(code, opts->cycles, opts->limit, SZ_D); + } check_alloc_code(code, MAX_INST_LEN*2); code_ptr jmp_off = code->cur+1; - jcc(code, CC_A, jmp_off+1); + jcc(code, CC_NS, jmp_off+1); call(code, opts->handle_cycle_limit); *jmp_off = code->cur - (jmp_off+1); } -- cgit v1.2.3