From 1f7eb1afff1a9b13cde11a786145ba313df3334a Mon Sep 17 00:00:00 2001 From: Michael Pavone Date: Sat, 2 Feb 2019 23:02:19 -0800 Subject: Implemented LDI in new Z80 core --- cpu_dsl.py | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'cpu_dsl.py') diff --git a/cpu_dsl.py b/cpu_dsl.py index b38a83b..c3f1f70 100755 --- a/cpu_dsl.py +++ b/cpu_dsl.py @@ -873,11 +873,19 @@ def _geuCImpl(prog, parent, fieldVals, output): params = [prog.resolveParam(p, parent, fieldVals) for p in prog.lastOp.params] return '\n\tif ({a} >= {b}) '.format(a=params[1], b = params[0]) + '{' else: - raise ion(">=U not implemented in the general case yet") + raise Exception(">=U not implemented in the general case yet") + +def _eqCImpl(prog, parent, fieldVals, output): + return '\n\tif (!{a}) {'.format(a=prog.resolveParam(prog.lastDst, None, {})) + +def _neqCImpl(prog, parent, fieldVals, output): + return '\n\tif ({a}) {'.format(a=prog.resolveParam(prog.lastDst, None, {})) _ifCmpImpl = { 'c': { - '>=U': _geuCImpl + '>=U': _geuCImpl, + '=': _eqCImpl, + '!=': _neqCImpl } } #represents a DSL conditional construct -- cgit v1.2.3