From 3127207249646a6c3fe54830fe969e2841b8ba52 Mon Sep 17 00:00:00 2001 From: Michael Pavone Date: Thu, 31 Jan 2019 23:03:51 -0800 Subject: Implemented the rest of the rotate instructions in new Z80 core --- cpu_dsl.py | 16 +++------------- 1 file changed, 3 insertions(+), 13 deletions(-) (limited to 'cpu_dsl.py') diff --git a/cpu_dsl.py b/cpu_dsl.py index 3806741..6c2ca15 100755 --- a/cpu_dsl.py +++ b/cpu_dsl.py @@ -326,6 +326,8 @@ def _updateFlagsCImpl(prog, params, rawParams): resultBit = prog.paramSize(prog.lastDst) - 1 elif calc == 'carry': resultBit = prog.paramSize(prog.lastDst) + if prog.lastOp.op == 'ror': + resultBit -= 1 elif calc == 'half': resultBit = prog.paramSize(prog.lastDst) - 4 myRes = '({a} ^ {b} ^ {res})'.format(a = prog.lastA, b = prog.lastB, res = lastDst) @@ -578,20 +580,8 @@ def _rlcCImpl(prog, params, rawParams, flagUpdates): ) def _rorCImpl(prog, params, rawParams, flagUpdates): - needsCarry = False - if flagUpdates: - for flag in flagUpdates: - calc = prog.flags.flagCalc[flag] - if calc == 'carry': - needsCarry = True - decl = '' size = prog.paramSize(rawParams[2]) - if needsCarry: - decl,name = prog.getTemp(size) - dst = prog.carryFlowDst = name - else: - dst = params[2] - return decl + '\n\t{dst} = {a} >> {b} | {a} << ({size} - {b});'.format(dst = dst, + return '\n\t{dst} = {a} >> {b} | {a} << ({size} - {b});'.format(dst = params[2], a = params[0], b = params[1], size=size ) -- cgit v1.2.3