From 53015149f581d73e44a75bb5322f8f803411a04e Mon Sep 17 00:00:00 2001 From: Michael Pavone Date: Sat, 2 Feb 2019 15:35:15 -0800 Subject: Implemented RES instruction in new Z80 core --- cpu_dsl.py | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'cpu_dsl.py') diff --git a/cpu_dsl.py b/cpu_dsl.py index 58b84b4..b38a83b 100755 --- a/cpu_dsl.py +++ b/cpu_dsl.py @@ -745,6 +745,13 @@ class NormalOp: output.append(_opMap['mov'].generate(otype, prog, shortProc, shortParams, None)) else: output.append(opDef.generate(otype, prog, procParams, self.params, flagUpdates)) + for dstIdx in opDef.outOp: + dst = self.params[dstIdx] + while dst in prog.meta: + dst = prog.meta[dst] + if dst in parent.regValues: + del parent.regValues[dst] + elif self.op in prog.subroutines: procParams = [] for param in self.params: -- cgit v1.2.3