From 717c5f6963f57ef01f707f5e6fa7ff6a37ce7240 Mon Sep 17 00:00:00 2001 From: Michael Pavone Date: Mon, 28 Jan 2019 19:24:04 -0800 Subject: Fix zero flag calculation in CPU DSL --- cpu_dsl.py | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) (limited to 'cpu_dsl.py') diff --git a/cpu_dsl.py b/cpu_dsl.py index 9c056d5..1f43203 100755 --- a/cpu_dsl.py +++ b/cpu_dsl.py @@ -324,14 +324,11 @@ def _updateFlagsCImpl(prog, params, rawParams): output.append('\n\t{reg} = {res} ? ({reg} & {mask}U) : ({reg} | {bit}U);'.format( reg = reg, mask = ~(1 << storageBit), res = lastDst, bit = 1 << storageBit )) - elif prog.paramSize(prog.lastDst) > prog.paramSize(storage): + else: reg = prog.resolveParam(storage, None, {}) - output.append('\n\t{reg} = {res} != 0;'.format( + output.append('\n\t{reg} = {res} == 0;'.format( reg = reg, res = lastDst )) - else: - reg = prog.resolveParam(storage, None, {}) - output.append('\n\t{reg} = {res};'.format(reg = reg, res = lastDst)) elif calc == 'half-carry': pass elif calc == 'carry': @@ -978,6 +975,7 @@ class Program: self.regs.writeHeader(otype, hFile) hFile.write('\n}} {0}context;'.format(self.prefix)) hFile.write('\n') + hFile.write('\nvoid {pre}execute({type} *context, uint32_t target_cycle);'.format(pre = self.prefix, type = self.context_type)) hFile.write('\n#endif //{0}_'.format(macro)) hFile.write('\n') hFile.close() -- cgit v1.2.3