From 822f91d0a3dd99351d881868f780058949099ffe Mon Sep 17 00:00:00 2001
From: Michael Pavone <pavone@retrodev.com>
Date: Sun, 3 Feb 2019 10:40:41 -0800
Subject: Implemented the rest of the block move instructions in new Z80 core

---
 cpu_dsl.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'cpu_dsl.py')

diff --git a/cpu_dsl.py b/cpu_dsl.py
index c3f1f70..062d2ac 100755
--- a/cpu_dsl.py
+++ b/cpu_dsl.py
@@ -167,7 +167,7 @@ class SubRoutine(Block):
 			self.args.append((name, size))
 		elif op.op == 'local':
 			name = op.params[0]
-			size = op.params[1]
+			size = int(op.params[1])
 			self.locals[name] = size
 		else:
 			self.implementation.append(op)
@@ -339,7 +339,7 @@ def _updateFlagsCImpl(prog, params, rawParams):
 		if prog.carryFlowDst:
 			lastDst = prog.carryFlowDst
 		else:
-			lastDst = prog.resolveParam(prog.lastDst, None, {})
+			lastDst = prog.resolveParam(prog.lastDst, prog.currentScope, {})
 		storage = prog.flags.getStorage(flag)
 		if calc == 'bit' or calc == 'sign' or calc == 'carry' or calc == 'half' or calc == 'overflow':
 			myRes = lastDst
-- 
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