From 84198d4ef6e5f311945ec6f6a8956426a52795af Mon Sep 17 00:00:00 2001
From: Michael Pavone <pavone@retrodev.com>
Date: Tue, 12 Feb 2019 09:58:04 -0800
Subject: Integration of new Z80 core is sort of working now

---
 cpu_dsl.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'cpu_dsl.py')

diff --git a/cpu_dsl.py b/cpu_dsl.py
index 605ce7a..e77fe34 100755
--- a/cpu_dsl.py
+++ b/cpu_dsl.py
@@ -696,7 +696,7 @@ _opMap = {
 	'sext': Op(_sext).addImplementation('c', 2, _sextCImpl),
 	'ocall': Op().addImplementation('c', None, lambda prog, params: '\n\t{pre}{fun}({args});'.format(
 		pre = prog.prefix, fun = params[0], args = ', '.join(['context'] + [str(p) for p in params[1:]])
-	)),
+	) + _updateSyncCImpl(prog, params)),
 	'cycles': Op().addImplementation('c', None,
 		lambda prog, params: '\n\tcontext->cycles += context->opts->gen.clock_divider * {0};'.format(
 			params[0]
-- 
cgit v1.2.3