From 961bdbea9dbbabff23624ef18280218eae452a3a Mon Sep 17 00:00:00 2001 From: Michael Pavone Date: Tue, 5 Feb 2019 19:29:54 -0800 Subject: Fixed half-carry flag calcuation for adc/sbc in new Z80 core --- cpu_dsl.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'cpu_dsl.py') diff --git a/cpu_dsl.py b/cpu_dsl.py index 9893600..928681b 100755 --- a/cpu_dsl.py +++ b/cpu_dsl.py @@ -545,7 +545,7 @@ def _adcCImpl(prog, params, rawParams, flagUpdates): decl,name = prog.getTemp(size) dst = prog.carryFlowDst = name prog.lastA = params[0] - prog.lastB = '({b} + ({check} ? 1 : 0))'.format(b = params[1], check = carryCheck) + prog.lastB = params[1] prog.lastBFlow = '(~{b})'.format(b=params[1]) else: dst = params[2] @@ -573,7 +573,7 @@ def _sbcCImpl(prog, params, rawParams, flagUpdates): decl,name = prog.getTemp(size) dst = prog.carryFlowDst = name prog.lastA = params[1] - prog.lastB = '({b} ^ ({check} ? 1 : 0))'.format(b = params[0], check = carryCheck) + prog.lastB = params[0] prog.lastBFlow = params[0] else: dst = params[2] -- cgit v1.2.3