From 0c1a8199f120d4e30c6ce311a49b0d06e0f6e3b5 Mon Sep 17 00:00:00 2001 From: Michael Pavone Date: Thu, 23 Apr 2020 20:57:28 -0700 Subject: Implement 68K and instruction in new core --- m68k.cpu | 62 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) (limited to 'm68k.cpu') diff --git a/m68k.cpu b/m68k.cpu index 9e33a31..91bd8ae 100644 --- a/m68k.cpu +++ b/m68k.cpu @@ -578,7 +578,69 @@ m68k_save_dst mov aregs.D scratch2 m68k_write_size Z 0 m68k_prefetch + +1100DDD0ZZMMMRRR and_ea_dn + invalid M 1 + invalid M 7 R 5 + invalid M 7 R 6 + invalid M 7 R 7 + invalid Z 3 + m68k_fetch_src_ea M R Z + and src dregs.D dregs.D Z + update_flags NZV0C0 + m68k_prefetch + +1100DDD1ZZMMMRRR and_dn_ea + invalid M 0 + invalid M 1 + invalid M 7 R 2 + invalid M 7 R 3 + invalid M 7 R 4 + invalid M 7 R 5 + invalid M 7 R 6 + invalid M 7 R 7 + invalid Z 3 + m68k_fetch_dst_ea M R Z + + and dregs.D dst dst Z + update_flags NZV0C0 + m68k_save_dst Z + m68k_prefetch + +00000010ZZMMMRRR andi + local immed 32 + invalid Z 3 + invalid M 1 + invalid M 7 R 2 + invalid M 7 R 3 + invalid M 7 R 4 + invalid M 7 R 5 + invalid M 7 R 6 + invalid M 7 R 7 + #fetch immediate operand + m68k_prefetch + switch Z + case 2 + lsl prefetch 16 immed + m68k_prefetch + or prefetch immed immed + default + mov prefetch immed + end + #fetch dst EA + m68k_fetch_dst_ea M R Z + + and immed dst dst Z + update_flags NZV0C0 + m68k_save_dst Z + m68k_prefetch + +0000001000111100 andi_to_ccr + #fetch immediate operand + m68k_prefetch + and prefetch ccr ccr + m68k_prefetch 00ZZRRRMMMEEESSS move invalid Z 0 -- cgit v1.2.3