From 217697e9a74ad442b40a079fe9c664d87eac9002 Mon Sep 17 00:00:00 2001 From: Michael Pavone Date: Thu, 11 May 2017 08:01:10 -0700 Subject: Fix regression in mode 4 introduced when advance_output_line was added --- vdp.c | 1 + 1 file changed, 1 insertion(+) (limited to 'vdp.c') diff --git a/vdp.c b/vdp.c index 22268f9..d7b98db 100644 --- a/vdp.c +++ b/vdp.c @@ -1972,6 +1972,7 @@ static void draw_right_border(vdp_context *context) context->cycles += slot_cycles;\ if ((slot+1) == LINE_CHANGE_MODE4) {\ vdp_advance_line(context);\ + advance_output_line(context);\ if (context->vcounter == 192) {\ return;\ }\ -- cgit v1.2.3