From 7f8e47eb7e81a7001f0c6a00f2cf52f1e50a96a2 Mon Sep 17 00:00:00 2001 From: Mike Pavone Date: Tue, 17 Sep 2013 00:42:49 -0700 Subject: Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40 --- vdp.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) (limited to 'vdp.c') diff --git a/vdp.c b/vdp.c index b75f063..5d02ce6 100644 --- a/vdp.c +++ b/vdp.c @@ -421,13 +421,13 @@ void external_slot(vdp_context * context) break; case CRAM_WRITE: { //printf("CRAM Write | %X to %X\n", start->value, (start->address/2) & (CRAM_SIZE-1)); - write_cram(context, start->address, start->value); + write_cram(context, start->address, start->partial == 2 ? context->fifo[context->fifo_write].value : start->value); break; } case VSRAM_WRITE: if (((start->address/2) & 63) < VSRAM_SIZE) { //printf("VSRAM Write: %X to %X\n", start->value, context->address); - context->vsram[(start->address/2) & 63] = start->value; + context->vsram[(start->address/2) & 63] = start->partial == 2 ? context->fifo[context->fifo_write].value : start->value; } break; @@ -1597,12 +1597,15 @@ uint16_t vdp_data_port_read(vdp_context * context) value = context->cram[(context->address/2) & (CRAM_SIZE-1)] & CRAM_BITS; value |= context->fifo[context->fifo_write].value & ~CRAM_BITS; break; - case VSRAM_READ: - if (((context->address / 2) & 63) < VSRAM_SIZE) { - value = context->vsram[(context->address / 2) & 63] & VSRAM_BITS; - value |= context->fifo[context->fifo_write].value & VSRAM_DIRTY_BITS; + case VSRAM_READ: { + uint16_t address = (context->address /2) & 63; + if (address >= VSRAM_SIZE) { + address = 0; } + value = context->vsram[address] & VSRAM_BITS; + value |= context->fifo[context->fifo_write].value & VSRAM_DIRTY_BITS; break; + } } context->address += context->regs[REG_AUTOINC]; return value; -- cgit v1.2.3