From 62a92e53aa6a9657ee6435ecbe2965de2f4b061a Mon Sep 17 00:00:00 2001 From: Michael Pavone Date: Tue, 29 Jan 2019 23:56:48 -0800 Subject: Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right --- z80_util.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'z80_util.c') diff --git a/z80_util.c b/z80_util.c index 58f763a..6a4a556 100644 --- a/z80_util.c +++ b/z80_util.c @@ -1,11 +1,13 @@ void z80_read_8(z80_context *context) { + context->cycles += 3 * context->opts->gen.clock_divider; context->scratch1 = read_byte(context->scratch1, NULL, &context->opts->gen, context); } void z80_write_8(z80_context *context) { + context->cycles += 3 * context->opts->gen.clock_divider; write_byte(context->scratch2, context->scratch1, NULL, &context->opts->gen, context); } -- cgit v1.2.3