From c32d616e1e014df30a8a50491b879e7599ba3243 Mon Sep 17 00:00:00 2001 From: Oxore Date: Sat, 6 May 2023 16:01:32 +0300 Subject: Add a bit of comments on Mode set 2 register macros --- vdp.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/vdp.cpp b/vdp.cpp index 930af09..6817c2d 100644 --- a/vdp.cpp +++ b/vdp.cpp @@ -9,6 +9,7 @@ #include #include +/// DISP: Enable (1) / Disable (0) Display #define MODESET2_DISP_MASK (1) #define MODESET2_DISP_SHIFT (6) #define MODESET2_DISP_GET(reg) \ @@ -17,6 +18,7 @@ ((reg) = ((reg) & ~(MODESET2_DISP_MASK << MODESET2_DISP_SHIFT)) \ | ((v & MODESET2_DISP_MASK) << MODESET2_DISP_SHIFT)) +/// IE0: Enable (1) / Disable (0) V interrupt (IRQ 6) #define MODESET2_IE0_MASK (1) #define MODESET2_IE0_SHIFT (5) #define MODESET2_IE0_GET(reg) \ @@ -25,6 +27,7 @@ ((reg) = ((reg) & ~(MODESET2_IE0_MASK << MODESET2_IE0_SHIFT)) \ | ((v & MODESET2_IE0_MASK) << MODESET2_IE0_SHIFT)) +/// M1: Enable (1) / Disable (0) DMA #define MODESET2_M1_MASK (1) #define MODESET2_M1_SHIFT (4) #define MODESET2_M1_GET(reg) \ @@ -33,6 +36,7 @@ ((reg) = ((reg) & ~(MODESET2_M1_MASK << MODESET2_M1_SHIFT)) \ | ((v & MODESET2_M1_MASK) << MODESET2_M1_SHIFT)) +/// M2: V 30 (1) / V 28 (0) cell mode (PAL mode, always 0 in NTSC mdoe) #define MODESET2_M2_MASK (1) #define MODESET2_M2_SHIFT (3) #define MODESET2_M2_GET(reg) \ -- cgit v1.2.3