From ea807de65b0485ac58b6eae576209c64d4d5c4e9 Mon Sep 17 00:00:00 2001 From: Oxore Date: Sun, 5 Mar 2023 20:20:45 +0300 Subject: Split app code and third party libraries --- Libraries/CMSIS/Device/Include/stm32f0xx.h | 5111 ---------------------------- 1 file changed, 5111 deletions(-) delete mode 100644 Libraries/CMSIS/Device/Include/stm32f0xx.h (limited to 'Libraries/CMSIS/Device/Include/stm32f0xx.h') diff --git a/Libraries/CMSIS/Device/Include/stm32f0xx.h b/Libraries/CMSIS/Device/Include/stm32f0xx.h deleted file mode 100644 index 53c8c01..0000000 --- a/Libraries/CMSIS/Device/Include/stm32f0xx.h +++ /dev/null @@ -1,5111 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx.h - * @author MCD Application Team - * @version V1.3.1 - * @date 17-January-2014 - * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. - * This file contains all the peripheral register's definitions, bits - * definitions and memory mapping for STM32F0xx devices. - * - * The file is the unique include file that the application programmer - * is using in the C source code, usually in main.c. This file contains: - * - Configuration section that allows to select: - * - The device used in the target application - * - To use or not the peripheral’s drivers in application code(i.e. - * code will be based on direct access to peripheral’s registers - * rather than drivers API), this option is controlled by - * "#define USE_STDPERIPH_DRIVER" - * - To change few application-specific parameters such as the HSE - * crystal frequency - * - Data structures and the address mapping for all peripherals - * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral’s registers hardware - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f0xx - * @{ - */ - -#ifndef __STM32F0XX_H -#define __STM32F0XX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup Library_configuration_section - * @{ - */ - -/* Uncomment the line below according to the target STM32F0 device used in your - application - */ - -#if !defined (STM32F030) && !defined (STM32F031) && !defined (STM32F051) && !defined (STM32F072) && !defined (STM32F042) - /* #define STM32F030 */ - /* #define STM32F031 */ - /* #define STM32F051 */ - #define STM32F072 - /* #define STM32F042 */ -#endif - -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - */ - -/* Old STM32F0XX definition, maintained for legacy purpose */ -#if defined(STM32F0XX) || defined(STM32F0XX_MD) - #define STM32F051 -#endif /* STM32F0XX */ - -/* Old STM32F0XX_LD definition, maintained for legacy purpose */ -#ifdef STM32F0XX_LD - #define STM32F031 -#endif /* STM32F0XX_LD */ - -/* Old STM32F0XX_HD definition, maintained for legacy purpose */ -#ifdef STM32F0XX_HD - #define STM32F072 -#endif /* STM32F0XX_HD */ - -/* Old STM32F030X6/X8 definition, maintained for legacy purpose */ -#if defined (STM32F030X8) || defined (STM32F030X6) - #define STM32F030 -#endif /* STM32F030X8 or STM32F030X6 */ - - -#if !defined (STM32F030) && !defined (STM32F031) && !defined (STM32F051) && !defined (STM32F072) && !defined (STM32F042) - #error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)" -#endif - -#if !defined USE_STDPERIPH_DRIVER -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ - /*#define USE_STDPERIPH_DRIVER*/ -#endif /* USE_STDPERIPH_DRIVER */ - -/** - * @brief In the following line adjust the value of External High Speed oscillator (HSE) - used in your application - - Tip: To avoid modifying this file each time you need to use different HSE, you - can define the HSE value in your toolchain compiler preprocessor. - */ -#if !defined (HSE_VALUE) -#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/ -#endif /* HSE_VALUE */ - -/** - * @brief In the following line adjust the External High Speed oscillator (HSE) Startup - Timeout value - */ -#if !defined (HSE_STARTUP_TIMEOUT) -#define HSE_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSE start up */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup - Timeout value - */ -#if !defined (HSI_STARTUP_TIMEOUT) -#define HSI_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSI start up */ -#endif /* HSI_STARTUP_TIMEOUT */ - -#if !defined (HSI_VALUE) -#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal High Speed oscillator in Hz. - The real value may vary depending on the variations - in voltage and temperature. */ -#endif /* HSI_VALUE */ - -#if !defined (HSI14_VALUE) -#define HSI14_VALUE ((uint32_t)14000000) /*!< Value of the Internal High Speed oscillator for ADC in Hz. - The real value may vary depending on the variations - in voltage and temperature. */ -#endif /* HSI14_VALUE */ - -#if !defined (HSI48_VALUE) -#define HSI48_VALUE ((uint32_t)48000000) /*!< Value of the Internal High Speed oscillator for USB in Hz. - The real value may vary depending on the variations - in voltage and temperature. */ -#endif /* HSI48_VALUE */ - -#if !defined (LSI_VALUE) -#define LSI_VALUE ((uint32_t)40000) /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ -#endif /* LSI_VALUE */ - -#if !defined (LSE_VALUE) -#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -/** - * @brief STM32F0xx Standard Peripheral Library version number V1.3.1 - */ -#define __STM32F0XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32F0XX_STDPERIPH_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ -#define __STM32F0XX_STDPERIPH_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ -#define __STM32F0XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32F0XX_STDPERIPH_VERSION ((__STM32F0XX_STDPERIPH_VERSION_MAIN << 24)\ - |(__STM32F0XX_STDPERIPH_VERSION_SUB1 << 16)\ - |(__STM32F0XX_STDPERIPH_VERSION_SUB2 << 8)\ - |(__STM32F0XX_STDPERIPH_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ - -/** - * @brief STM32F0xx Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ -#define __CM0_REV 0 /*!< Core Revision r0p0 */ -#define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */ -#define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/*!< Interrupt Number Definition */ -typedef enum IRQn -{ -/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ - -#if defined (STM32F051) -/****** STM32F051 specific Interrupt Numbers *************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */ - RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ - FLASH_IRQn = 3, /*!< FLASH Interrupt */ - RCC_IRQn = 4, /*!< RCC Interrupt */ - EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ - EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ - EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ - TS_IRQn = 8, /*!< Touch sense controller Interrupt */ - DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ - DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ - DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */ - ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */ - TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ - TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 15, /*!< TIM2 Interrupt */ - TIM3_IRQn = 16, /*!< TIM3 Interrupt */ - TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */ - TIM14_IRQn = 19, /*!< TIM14 Interrupt */ - TIM15_IRQn = 20, /*!< TIM15 Interrupt */ - TIM16_IRQn = 21, /*!< TIM16 Interrupt */ - TIM17_IRQn = 22, /*!< TIM17 Interrupt */ - I2C1_IRQn = 23, /*!< I2C1 Interrupt */ - I2C2_IRQn = 24, /*!< I2C2 Interrupt */ - SPI1_IRQn = 25, /*!< SPI1 Interrupt */ - SPI2_IRQn = 26, /*!< SPI2 Interrupt */ - USART1_IRQn = 27, /*!< USART1 Interrupt */ - USART2_IRQn = 28, /*!< USART2 Interrupt */ - CEC_IRQn = 30 /*!< CEC Interrupt */ -#elif defined (STM32F031) -/****** STM32F031 specific Interrupt Numbers *************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */ - RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ - FLASH_IRQn = 3, /*!< FLASH Interrupt */ - RCC_IRQn = 4, /*!< RCC Interrupt */ - EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ - EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ - EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ - DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ - DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ - DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */ - ADC1_IRQn = 12, /*!< ADC1 Interrupt */ - TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ - TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 15, /*!< TIM2 Interrupt */ - TIM3_IRQn = 16, /*!< TIM3 Interrupt */ - TIM14_IRQn = 19, /*!< TIM14 Interrupt */ - TIM16_IRQn = 21, /*!< TIM16 Interrupt */ - TIM17_IRQn = 22, /*!< TIM17 Interrupt */ - I2C1_IRQn = 23, /*!< I2C1 Interrupt */ - SPI1_IRQn = 25, /*!< SPI1 Interrupt */ - USART1_IRQn = 27 /*!< USART1 Interrupt */ -#elif defined (STM32F030) -/****** STM32F030 specific Interrupt Numbers *************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ - FLASH_IRQn = 3, /*!< FLASH Interrupt */ - RCC_IRQn = 4, /*!< RCC Interrupt */ - EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ - EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ - EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ - DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ - DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ - DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */ - ADC1_IRQn = 12, /*!< ADC1 Interrupt */ - TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ - TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ - TIM3_IRQn = 16, /*!< TIM3 Interrupt */ - TIM14_IRQn = 19, /*!< TIM14 Interrupt */ - TIM15_IRQn = 20, /*!< TIM15 Interrupt */ - TIM16_IRQn = 21, /*!< TIM16 Interrupt */ - TIM17_IRQn = 22, /*!< TIM17 Interrupt */ - I2C1_IRQn = 23, /*!< I2C1 Interrupt */ - I2C2_IRQn = 24, /*!< I2C2 Interrupt */ - SPI1_IRQn = 25, /*!< SPI1 Interrupt */ - SPI2_IRQn = 26, /*!< SPI2 Interrupt */ - USART1_IRQn = 27, /*!< USART1 Interrupt */ - USART2_IRQn = 28 /*!< USART2 Interrupt */ -#elif defined (STM32F072) - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_VDDIO2_IRQn = 1, /*!< PVD and VDDIO2 supply comparator through EXTI Line detect Interrupt */ - RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ - FLASH_IRQn = 3, /*!< FLASH Interrupt */ - RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */ - EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ - EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ - EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ - TSC_IRQn = 8, /*!< TSC Interrupt */ - DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ - DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ - DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */ - ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */ - TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ - TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 15, /*!< TIM2 Interrupt */ - TIM3_IRQn = 16, /*!< TIM3 Interrupt */ - TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */ - TIM7_IRQn = 18, /*!< TIM7 Interrupts */ - TIM14_IRQn = 19, /*!< TIM14 Interrupt */ - TIM15_IRQn = 20, /*!< TIM15 Interrupt */ - TIM16_IRQn = 21, /*!< TIM16 Interrupt */ - TIM17_IRQn = 22, /*!< TIM17 Interrupt */ - I2C1_IRQn = 23, /*!< I2C1 Interrupt */ - I2C2_IRQn = 24, /*!< I2C2 Interrupt */ - SPI1_IRQn = 25, /*!< SPI1 Interrupt */ - SPI2_IRQn = 26, /*!< SPI2 Interrupt */ - USART1_IRQn = 27, /*!< USART1 Interrupt */ - USART2_IRQn = 28, /*!< USART2 Interrupt */ - USART3_4_IRQn = 29, /*!< USART3 and USART4 Interrupts */ - CEC_CAN_IRQn = 30, /*!< CEC and CAN Interrupts */ - USB_IRQn = 31 /*!< USB Low Priority global Interrupt */ -#elif defined (STM32F042) - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_VDDIO2_IRQn = 1, /*!< PVD and VDDIO2 supply comparator through EXTI Line detect Interrupt */ - RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ - FLASH_IRQn = 3, /*!< FLASH Interrupt */ - RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */ - EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ - EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ - EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ - TSC_IRQn = 8, /*!< TSC Interrupt */ - DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ - DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ - DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4, Channel 5 Interrupts */ - ADC1_IRQn = 12, /*!< ADC1 Interrupts */ - TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ - TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 15, /*!< TIM2 Interrupt */ - TIM3_IRQn = 16, /*!< TIM3 Interrupt */ - TIM14_IRQn = 19, /*!< TIM14 Interrupt */ - TIM16_IRQn = 21, /*!< TIM16 Interrupt */ - TIM17_IRQn = 22, /*!< TIM17 Interrupt */ - I2C1_IRQn = 23, /*!< I2C1 Interrupt */ - SPI1_IRQn = 25, /*!< SPI1 Interrupt */ - SPI2_IRQn = 26, /*!< SPI2 Interrupt */ - USART1_IRQn = 27, /*!< USART1 Interrupt */ - USART2_IRQn = 28, /*!< USART2 Interrupt */ - CEC_CAN_IRQn = 30, /*!< CEC and CAN Interrupts */ - USB_IRQn = 31 /*!< USB Low Priority global Interrupt */ -#endif /* STM32F051 */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm0.h" -#include "system_stm32f0xx.h" -#include - -/** @addtogroup Exported_types - * @{ - */ - -typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; - -typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */ - __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */ - __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */ - __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */ - __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */ - __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */ - uint32_t RESERVED3; /*!< Reserved, 0x24 */ - __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */ - uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ - __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CCR; -} ADC_Common_TypeDef; - - -/** - * @brief Controller Area Network TxMailBox - */ -typedef struct -{ - __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ - __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ - __IO uint32_t TDLR; /*!< CAN mailbox data low register */ - __IO uint32_t TDHR; /*!< CAN mailbox data high register */ -} CAN_TxMailBox_TypeDef; - -/** - * @brief Controller Area Network FIFOMailBox - */ -typedef struct -{ - __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ - __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ - __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ - __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ -} CAN_FIFOMailBox_TypeDef; - -/** - * @brief Controller Area Network FilterRegister - */ -typedef struct -{ - __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ - __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ -} CAN_FilterRegister_TypeDef; - -/** - * @brief Controller Area Network - */ -typedef struct -{ - __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ - __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ - __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ - __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ - __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ - __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ - __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ - __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ - uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ - CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ - CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ - uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ - __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ - __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ - uint32_t RESERVED2; /*!< Reserved, 0x208 */ - __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ - uint32_t RESERVED3; /*!< Reserved, 0x210 */ - __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ - uint32_t RESERVED4; /*!< Reserved, 0x218 */ - __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ - uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ - CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ -} CAN_TypeDef; - -/** - * @brief HDMI-CEC - */ - -typedef struct -{ - __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ - __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ - __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ - __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ - __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ - __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ -}CEC_TypeDef; - -/** - * @brief Comparator - */ - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x1C */ -} COMP_TypeDef; - - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - uint8_t RESERVED0; /*!< Reserved, 0x05 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ - uint32_t RESERVED2; /*!< Reserved, 0x0C */ - __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ - __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ -} CRC_TypeDef; - -/** - * @brief Clock Recovery System - */ -typedef struct -{ -__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ -__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ -__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ -__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ -} CRS_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ -} DMA_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!