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authorMichael Pavone <pavone@retrodev.com>2016-07-27 22:46:22 -0700
committerMichael Pavone <pavone@retrodev.com>2016-07-27 22:46:22 -0700
commit4fc2cd522e1487ba69cdfc2c40c54f2c0ca51797 (patch)
tree8d710f59ea880ab5eb060a5778e4ffaac202a802 /backend_x86.c
parent10ba33e23d93913721acbc9c68da229cdd45606e (diff)
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Diffstat (limited to 'backend_x86.c')
-rw-r--r--backend_x86.c22
1 files changed, 17 insertions, 5 deletions
diff --git a/backend_x86.c b/backend_x86.c
index 0619dd7..2c9f083 100644
--- a/backend_x86.c
+++ b/backend_x86.c
@@ -3,15 +3,23 @@
void cycles(cpu_options *opts, uint32_t num)
{
- add_ir(&opts->code, num*opts->clock_divider, opts->cycles, SZ_D);
+ if (opts->limit < 0) {
+ sub_ir(&opts->code, num*opts->clock_divider, opts->cycles, SZ_D);
+ } else {
+ add_ir(&opts->code, num*opts->clock_divider, opts->cycles, SZ_D);
+ }
}
void check_cycles_int(cpu_options *opts, uint32_t address)
{
code_info *code = &opts->code;
- cmp_rr(code, opts->cycles, opts->limit, SZ_D);
+ if (opts->limit < 0) {
+ or_rr(code, opts->cycles, opts->cycles, SZ_D);
+ } else {
+ cmp_rr(code, opts->cycles, opts->limit, SZ_D);
+ }
code_ptr jmp_off = code->cur+1;
- jcc(code, CC_A, jmp_off+1);
+ jcc(code, CC_NS, jmp_off+1);
mov_ir(code, address, opts->scratch1, SZ_D);
call(code, opts->handle_cycle_limit_int);
*jmp_off = code->cur - (jmp_off+1);
@@ -20,10 +28,14 @@ void check_cycles_int(cpu_options *opts, uint32_t address)
void check_cycles(cpu_options * opts)
{
code_info *code = &opts->code;
- cmp_rr(code, opts->cycles, opts->limit, SZ_D);
+ if (opts->limit < 0) {
+ or_rr(code, opts->cycles, opts->cycles, SZ_D);
+ } else {
+ cmp_rr(code, opts->cycles, opts->limit, SZ_D);
+ }
check_alloc_code(code, MAX_INST_LEN*2);
code_ptr jmp_off = code->cur+1;
- jcc(code, CC_A, jmp_off+1);
+ jcc(code, CC_NS, jmp_off+1);
call(code, opts->handle_cycle_limit);
*jmp_off = code->cur - (jmp_off+1);
}