Somewhat buggy implementations of shift instructions in new 68K core

1 files changed, 1 insertions, 1 deletions

diff --git a/cpu_dsl.py b/cpu_dsl.py
index f58749c..44e08fe 100755
--- a/cpu_dsl.py
+++ b/cpu_dsl.py
@@ -899,7 +899,7 @@ class NormalOp:
 			else:
 				param = parent.resolveLocal(param) or param
 				if param in fieldVals:
-					param = fieldVals[index]
+					param = fieldVals[param]
 			prog.meta[self.params[0]] = param
 		elif self.op == 'dis':
 			#TODO: Disassembler