Создаю новый репозиторий. Программа для версии NixieClock_v2. Работает, часы тикают. Есть проблема, что скачет вторая сеносрная кнопка (она в другом канале). Поэтому на нее собираюсь сделать антидребезг.

2 files changed, 727 insertions, 0 deletions

diff --git a/Libraries/CMSIS/Device/Source/Templates/iar/startup_stm32f072.s b/Libraries/CMSIS/Device/Source/Templates/iar/startup_stm32f072.s
new file mode 100644
index 0000000..6e07b0d
--- /dev/null
+++ b/Libraries/CMSIS/Device/Source/Templates/iar/startup_stm32f072.s
@@ -0,0 +1,369 @@
+;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
+;* File Name          : startup_stm32f072.s
+;* Author             : MCD Appl&ication Team
+;* Version            : V1.5.0
+;* Date               : 24-December-2014 
+;* Description        : STM32F072 Devices Devices vector table for 
+;*                      EWARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR 
+;*                        address.
+;*                      After Reset the Cortex-M0 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;  @attention
+; 
+;  Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+;  You may not use this file except in compliance with the License.
+;  You may obtain a copy of the License at:
+; 
+;         http://www.st.com/software_license_agreement_liberty_v2
+; 
+;  Unless required by applicable law or agreed to in writing, software 
+;  distributed under the License is distributed on an "AS IS" BASIS, 
+;  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;  See the License for the specific language governing permissions and
+;  limitations under the License.
+; 
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                  ; Reset Handler
+
+        DCD     NMI_Handler                    ; NMI Handler
+        DCD     HardFault_Handler              ; Hard Fault Handler
+        DCD     0                              ; Reserved
+        DCD     0                              ; Reserved
+        DCD     0                              ; Reserved
+        DCD     0                              ; Reserved
+        DCD     0                              ; Reserved
+        DCD     0                              ; Reserved
+        DCD     0                              ; Reserved
+        DCD     SVC_Handler                    ; SVCall Handler
+        DCD     0                              ; Reserved
+        DCD     0                              ; Reserved
+        DCD     PendSV_Handler                 ; PendSV Handler
+        DCD     SysTick_Handler                ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                ; Window Watchdog
+        DCD     PVD_VDDIO2_IRQHandler          ; PVD and VDDIO2 through EXTI Line detect
+        DCD     RTC_IRQHandler                 ; RTC through EXTI Line
+        DCD     FLASH_IRQHandler               ; FLASH
+        DCD     RCC_CRS_IRQHandler             ; RCC and CRS
+        DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
+        DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
+        DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
+        DCD     TSC_IRQHandler                  ; TS
+        DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
+        DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
+        DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
+        DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
+        DCD     TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
+        DCD     TIM1_CC_IRQHandler             ; TIM1 Capture Compare
+        DCD     TIM2_IRQHandler                ; TIM2
+        DCD     TIM3_IRQHandler                ; TIM3
+        DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
+        DCD     TIM7_IRQHandler                ; TIM7
+        DCD     TIM14_IRQHandler               ; TIM14
+        DCD     TIM15_IRQHandler               ; TIM15
+        DCD     TIM16_IRQHandler               ; TIM16
+        DCD     TIM17_IRQHandler               ; TIM17
+        DCD     I2C1_IRQHandler                ; I2C1
+        DCD     I2C2_IRQHandler                ; I2C2
+        DCD     SPI1_IRQHandler                ; SPI1
+        DCD     SPI2_IRQHandler                ; SPI2
+        DCD     USART1_IRQHandler              ; USART1
+        DCD     USART2_IRQHandler              ; USART2
+        DCD     USART3_4_IRQHandler            ; USART3 and USART4
+        DCD     CEC_CAN_IRQHandler             ; CEC and CAN
+        DCD     USB_IRQHandler                 ; USB
+        
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+        LDR     R0, =sfe(CSTACK)          ; set stack pointer 
+        MSR     MSP, R0 
+
+;;Check if boot space corresponds to test memory 
+        LDR R0,=0x00000004
+        LDR R1, [R0]
+        LSRS R1, R1, #24
+        LDR R2,=0x1F
+        CMP R1, R2
+        
+        BNE ApplicationStart       
+;; SYSCFG clock enable         
+        LDR R0,=0x40021018 
+        LDR R1,=0x00000001
+        STR R1, [R0]
+        
+;; Set CFGR1 register with flash memory remap at address 0
+
+        LDR R0,=0x40010000 
+        LDR R1,=0x00000000
+        STR R1, [R0]
+ApplicationStart
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+        
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+        
+        
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+       
+        
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+       
+        
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+        
+        
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+        
+        
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+        
+                
+        PUBWEAK PVD_VDDIO2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_VDDIO2_IRQHandler
+        B PVD_VDDIO2_IRQHandler
+        
+                
+        PUBWEAK RTC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_IRQHandler
+        B RTC_IRQHandler
+        
+                
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+        
+                
+        PUBWEAK RCC_CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_CRS_IRQHandler
+        B RCC_CRS_IRQHandler
+        
+                
+        PUBWEAK EXTI0_1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_1_IRQHandler
+        B EXTI0_1_IRQHandler
+        
+                
+        PUBWEAK EXTI2_3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_3_IRQHandler
+        B EXTI2_3_IRQHandler
+        
+                
+        PUBWEAK EXTI4_15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_15_IRQHandler
+        B EXTI4_15_IRQHandler
+        
+                
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+        
+                
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+        
+                
+        PUBWEAK DMA1_Channel2_3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_3_IRQHandler
+        B DMA1_Channel2_3_IRQHandler
+        
+                
+        PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_5_6_7_IRQHandler
+        B DMA1_Channel4_5_6_7_IRQHandler
+        
+                
+        PUBWEAK ADC1_COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_COMP_IRQHandler
+        B ADC1_COMP_IRQHandler
+        
+                 
+        PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_UP_TRG_COM_IRQHandler
+        B TIM1_BRK_UP_TRG_COM_IRQHandler
+        
+                
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+        
+                
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+        
+                
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+        
+                
+        PUBWEAK TIM6_DAC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+        B TIM6_DAC_IRQHandler
+        
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+        B TIM7_IRQHandler
+
+        PUBWEAK TIM14_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM14_IRQHandler
+        B TIM14_IRQHandler
+        
+                
+        PUBWEAK TIM15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+        B TIM15_IRQHandler
+        
+                
+        PUBWEAK TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+        B TIM16_IRQHandler
+        
+                
+        PUBWEAK TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+        B TIM17_IRQHandler
+        
+                
+        PUBWEAK I2C1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_IRQHandler
+        B I2C1_IRQHandler
+        
+                
+        PUBWEAK I2C2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_IRQHandler
+        B I2C2_IRQHandler
+        
+                
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+        
+                
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+        
+                
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+        
+                
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+        
+
+        PUBWEAK USART3_4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_4_IRQHandler
+        B USART3_4_IRQHandler
+        
+        
+        PUBWEAK CEC_CAN_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CEC_CAN_IRQHandler
+        B CEC_CAN_IRQHandler
+
+        PUBWEAK USB_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_IRQHandler
+        B USB_IRQHandler
+        
+        END
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Libraries/CMSIS/Device/Source/Templates/system_stm32f0xx.c b/Libraries/CMSIS/Device/Source/Templates/system_stm32f0xx.c
new file mode 100644
index 0000000..e05ebe2
--- /dev/null
+++ b/Libraries/CMSIS/Device/Source/Templates/system_stm32f0xx.c
@@ -0,0 +1,358 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f0xx.c
+  * @author  MCD Application Team
+  * @version V1.3.1
+  * @date    17-January-2014
+  * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
+  *          This file contains the system clock configuration for STM32F0xx devices,
+  *          and is generated by the clock configuration tool  
+  *          STM32F0xx_Clock_Configuration_V1.0.0.xls
+  *
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      and Divider factors, AHB/APBx prescalers and Flash settings),
+  *                      depending on the configuration made in the clock xls tool.
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f0xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (8 MHz Range) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
+  *    in "stm32f0xx.h" file. When HSE is used as system clock source, directly or
+  *    through PLL, and you are using different crystal you have to adapt the HSE
+  *    value to your own configuration.
+  *
+  * 5. This file configures the system clock as follows:
+  *=============================================================================
+  *                         System Clock Configuration
+  *=============================================================================
+  *        System Clock source          | PLL(HSE)
+  *-----------------------------------------------------------------------------
+  *        SYSCLK                       | 48000000 Hz
+  *-----------------------------------------------------------------------------
+  *        HCLK                         | 48000000 Hz
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler               | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler               | 1
+  *-----------------------------------------------------------------------------
+  *        HSE Frequency                | 8000000 Hz
+  *-----------------------------------------------------------------------------
+  *        PLL MUL                      | 6
+  *-----------------------------------------------------------------------------
+  *        VDD                          | 3.3 V
+  *-----------------------------------------------------------------------------
+  *        Flash Latency                | 1 WS
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f0xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F0xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f0xx.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F0xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F0xx_System_Private_Defines
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F0xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F0xx_System_Private_Variables
+  * @{
+  */
+uint32_t SystemCoreClock    = 48000000;
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F0xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{    
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+#if defined (STM32F031) || defined (STM32F072) || defined (STM32F042) 
+  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
+  RCC->CFGR &= (uint32_t)0xF8FFB80C;
+#else
+  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
+  RCC->CFGR &= (uint32_t)0x08FFB80C;
+#endif /* STM32F031*/
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
+  RCC->CFGR &= (uint32_t)0xFFC0FFFF;
+
+  /* Reset PREDIV1[3:0] bits */
+  RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
+
+  /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */
+  RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
+
+  /* Reset HSI14 bit */
+  RCC->CR2 &= (uint32_t)0xFFFFFFFE;
+
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
+
+  /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
+  SetSysClock();
+}
+
+/**
+  * @brief  Update SystemCoreClock according to Clock Register Values
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) HSI_VALUE is a constant defined in stm32f0xx.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSE_VALUE is a constant defined in stm32f0xx.h file (default value
+  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+        /* HSE oscillator clock selected as PREDIV1 clock entry */
+        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+      }      
+      break;
+    default: /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+/**
+  * @brief  Configures the System clock frequency, AHB/APBx prescalers and Flash
+  *         settings.
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer and set Flash Latency */
+    FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;
+
+    /* PLL configuration = HSE * 6 = 48 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6);
+            
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }  
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/