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authorOxore <oxore@protonmail.com>2023-03-05 20:20:45 +0300
committerOxore <oxore@protonmail.com>2023-03-05 20:20:45 +0300
commitea807de65b0485ac58b6eae576209c64d4d5c4e9 (patch)
treeb4264d20e1d700cfd9e0ece9d847a825dd1dfc03 /app/ltimers/ltimers_config.c
parentdd01e7ed22cea652061f0d12cecf929e04b285e9 (diff)
Split app code and third party libraries
Diffstat (limited to 'app/ltimers/ltimers_config.c')
-rw-r--r--app/ltimers/ltimers_config.c56
1 files changed, 56 insertions, 0 deletions
diff --git a/app/ltimers/ltimers_config.c b/app/ltimers/ltimers_config.c
new file mode 100644
index 0000000..a30b36f
--- /dev/null
+++ b/app/ltimers/ltimers_config.c
@@ -0,0 +1,56 @@
+#include "ltimers_config.h"
+
+#include "stm32f0xx_conf.h"
+
+
+// ----------------------------------------------------------------------------
+// Инициализация аппаратного таймера для генерирования прерываний каждую 1мс
+// ----------------------------------------------------------------------------
+void LTimersConfig ( void )
+{
+ NVIC_InitTypeDef NVIC_InitStructure;
+ TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
+
+ /* LTIMER_TIMx clock enable */
+ LTIMER_RCC_APBxPeriphClockCmd ( LTIMER_TIM_RCC, ENABLE );
+
+ /* Enable the LTIMER_TIMx gloabal Interrupt */
+ NVIC_InitStructure.NVIC_IRQChannel = LTIMER_TIM_IRQx;
+ NVIC_InitStructure.NVIC_IRQChannelPriority = 1;
+ NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+ NVIC_Init ( &NVIC_InitStructure );
+
+ /* -----------------------------------------------------------------------
+ In this example TIM7 counter clock (TIM7CLK) is set to APB1 clock (PCLK1), since
+ APB1 prescaler is set to 1 and TIM7 prescaler is set to 0.
+
+ In this example TIM7 input clock (TIM7CLK) is set to APB1 clock (PCLK1),
+ since APB1 prescaler is set to 1.
+ TIM7CLK = PCLK1 = HCLK = SystemCoreClock
+
+ With Prescaler set to 479 and Period to 24999, the TIM7 counter is updated each 250 ms
+ (i.e. and interrupt is generated each 250 ms)
+ TIM7 counter clock = TIM7CLK /((Prescaler + 1)*(Period + 1))
+ = 48 MHz / ((25000)*(480))
+ = 4 Hz
+ ==> TIM7 counter period = 250 ms
+
+ Note:
+ SystemCoreClock variable holds HCLK frequency and is defined in system_stm32f0xx.c file.
+ Each time the core clock (HCLK) changes, user had to call SystemCoreClockUpdate()
+ function to update SystemCoreClock variable value. Otherwise, any configuration
+ based on this variable will be incorrect.
+ ----------------------------------------------------------------------- */
+ /* Time base configuration */
+ TIM_TimeBaseStructure.TIM_Period = 1000; //24999;
+ TIM_TimeBaseStructure.TIM_Prescaler = (SystemCoreClock/1000000)-1; //479;
+ TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1;
+ TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
+ TIM_TimeBaseInit ( LTIMER_TIMx, &TIM_TimeBaseStructure );
+
+ /* LTIMER_TIMx Interrupts enable */
+ TIM_ITConfig ( LTIMER_TIMx, TIM_IT_Update, ENABLE );
+
+ /* LTIMER_TIMx enable counter */
+ TIM_Cmd ( LTIMER_TIMx, ENABLE );
+}