diff options
author | Oxore <oxore@protonmail.com> | 2023-03-05 20:20:45 +0300 |
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committer | Oxore <oxore@protonmail.com> | 2023-03-05 20:20:45 +0300 |
commit | ea807de65b0485ac58b6eae576209c64d4d5c4e9 (patch) | |
tree | b4264d20e1d700cfd9e0ece9d847a825dd1dfc03 /third_party/TouchSense/STMTouch_Driver/src/tsl_time_stm32f0xx.c | |
parent | dd01e7ed22cea652061f0d12cecf929e04b285e9 (diff) |
Split app code and third party libraries
Diffstat (limited to 'third_party/TouchSense/STMTouch_Driver/src/tsl_time_stm32f0xx.c')
-rw-r--r-- | third_party/TouchSense/STMTouch_Driver/src/tsl_time_stm32f0xx.c | 107 |
1 files changed, 107 insertions, 0 deletions
diff --git a/third_party/TouchSense/STMTouch_Driver/src/tsl_time_stm32f0xx.c b/third_party/TouchSense/STMTouch_Driver/src/tsl_time_stm32f0xx.c new file mode 100644 index 0000000..4db154a --- /dev/null +++ b/third_party/TouchSense/STMTouch_Driver/src/tsl_time_stm32f0xx.c @@ -0,0 +1,107 @@ +/** + ****************************************************************************** + * @file tsl_time_stm32f0xx.c + * @author MCD Application Team + * @version V1.4.4 + * @date 31-March-2014 + * @brief This file contains all functions to manage the timing with STM32F0xx products. + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "tsl_time_stm32f0xx.h" +#include "stm32f0xx_misc.h" +#include "stm32f0xx_rtc.h" +#include "stm32f0xx_tim.h" + +/* Private typedefs ----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private functions prototype -----------------------------------------------*/ + +/** + * @brief Initialization of the timing module. + * @param None + * @retval Status Return TSL_STATUS_ERROR if the Systick configuration has failed. + */ +TSL_Status_enum_T TSL_tim_Init(void) +{ + // Program one systick interrupt every (1 / TSLPRM_TICK_FREQ) ms +// if (SysTick_Config(SystemCoreClock / TSLPRM_TICK_FREQ)) +// { +// return TSL_STATUS_ERROR; +// } +// else +// { +// return TSL_STATUS_OK; +// } + + NVIC_InitTypeDef NVIC_InitStructure; + TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; + + /* TouchSense_TIMx clock enable */ + TS_RCC_APBxPeriphClockCmd ( TS_TIM_RCC, ENABLE ); + + /* Enable the TouchSense_TIMx gloabal Interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = TS_TIM_IRQx; + NVIC_InitStructure.NVIC_IRQChannelPriority = 1; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init ( &NVIC_InitStructure ); + + /* ----------------------------------------------------------------------- + In this example TIM7 counter clock (TIM7CLK) is set to APB1 clock (PCLK1), since + APB1 prescaler is set to 1 and TIM7 prescaler is set to 0. + + In this example TIM7 input clock (TIM7CLK) is set to APB1 clock (PCLK1), + since APB1 prescaler is set to 1. + TIM7CLK = PCLK1 = HCLK = SystemCoreClock + + With Prescaler set to 479 and Period to 24999, the TIM7 counter is updated each 250 ms + (i.e. and interrupt is generated each 250 ms) + TIM7 counter clock = TIM7CLK /((Prescaler + 1)*(Period + 1)) + = 48 MHz / ((25000)*(480)) + = 4 Hz + ==> TIM7 counter period = 250 ms + + Note: + SystemCoreClock variable holds HCLK frequency and is defined in system_stm32f0xx.c file. + Each time the core clock (HCLK) changes, user had to call SystemCoreClockUpdate() + function to update SystemCoreClock variable value. Otherwise, any configuration + based on this variable will be incorrect. + ----------------------------------------------------------------------- */ + + /* Time base configuration */ + TIM_TimeBaseStructure.TIM_Period = 1000; // Это миксросекунды //24999 + TIM_TimeBaseStructure.TIM_Prescaler = (SystemCoreClock/1000000)-1; //479; + TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1; + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInit ( TS_TIMx, &TIM_TimeBaseStructure ); + + /* TouchSense_TIMx Interrupts enable */ + TIM_ITConfig ( TS_TIMx, TIM_IT_Update, ENABLE ); + + /* TouchSense_TIMx enable counter */ + TIM_Cmd ( TS_TIMx, ENABLE ); + + return TSL_STATUS_OK; +} + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |