10 files changed, 988 insertions, 0 deletions
diff --git a/bench/vhdl/AsyncLog.vhd b/bench/vhdl/AsyncLog.vhd
new file mode 100644
index 0000000..04a6a4d
--- /dev/null
+++ b/bench/vhdl/AsyncLog.vhd
@@ -0,0 +1,124 @@
+--
+-- Asynchronous serial input with binary file log
+--
+-- Version : 0146
+--
+-- Copyright (c) 2001 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--	http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity AsyncLog is
+	generic(
+		FileName		: string;
+		Baud			: integer;
+		Bits			: integer := 8;		-- Data bits
+		Parity			: boolean := false;	-- Enable Parity
+		P_Odd_Even_n	: boolean := false	-- false => Even Parity, true => Odd Parity
+	);
+	port(
+		RXD				: in std_logic
+	);
+end AsyncLog;
+
+architecture behaviour of AsyncLog is
+
+	function to_char(
+		constant Byte : std_logic_vector(7 downto 0)
+	) return character is
+	begin
+		return character'val(to_integer(unsigned(Byte)));
+	end function;
+
+	signal	Baud16			: std_logic := '0';
+
+	-- Receive signals
+	signal	Bit_Phase		: unsigned(3 downto 0) := "0000";
+	signal	RX_ShiftReg		: std_logic_vector(Bits - 1 downto 0) := (others => '0');
+	signal	RX_Bit_Cnt		: integer := 0;
+	signal	ParTmp			: boolean;
+
+begin
+
+	Baud16 <= not Baud16 after 1000000000 ns / 32 / Baud;
+
+	process (Baud16)
+		type ChFile is file of character;
+		file OutFile : ChFile open write_mode is FileName;
+	begin
+		if Baud16'event and Baud16 = '1' then
+			if RX_Bit_Cnt = 0 and (RXD = '1' or Bit_Phase = "0111") then
+				Bit_Phase <= "0000";
+			else
+				Bit_Phase <= Bit_Phase + 1;
+			end if;
+			if RX_Bit_Cnt = 0 then
+				if Bit_Phase = "0111" then
+					RX_Bit_Cnt <= RX_Bit_Cnt + 1;
+				end if;
+				ParTmp <= false;
+			elsif Bit_Phase = "1111" then
+				RX_Bit_Cnt <= RX_Bit_Cnt + 1;
+				if (RX_Bit_Cnt = Bits + 1 and not Parity) or
+					(RX_Bit_Cnt = Bits + 2 and Parity) then -- Stop bit
+					RX_Bit_Cnt <= 0;
+					assert RXD = '1'
+						report "Framing error"
+						severity error;
+					write(OutFile, to_char(RX_ShiftReg(7 downto 0)));
+				elsif RX_Bit_Cnt = Bits + 1 and Parity then -- Parity bit
+					assert ParTmp xor (RXD = '1') = P_Odd_Even_n
+						report "Parity error"
+						severity error;
+				else
+					ParTmp <= ParTmp xor (RXD = '1');
+					RX_ShiftReg(Bits - 2 downto 0) <= RX_ShiftReg(Bits - 1 downto 1);
+					RX_ShiftReg(Bits - 1) <= RXD;
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
+
diff --git a/bench/vhdl/AsyncStim.vhd b/bench/vhdl/AsyncStim.vhd
new file mode 100644
index 0000000..04834e4
--- /dev/null
+++ b/bench/vhdl/AsyncStim.vhd
@@ -0,0 +1,115 @@
+--
+-- Asynchronous serial generator with input from binary file
+--
+-- Version : 0146
+--
+-- Copyright (c) 2001 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--	http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity AsyncStim is
+	generic(
+		FileName		: string;
+		Baud			: integer;
+		InterCharDelay	: time := 0 ns;
+		Bits			: integer := 8;		-- Data bits
+		Parity			: boolean := false;	-- Enable Parity
+		P_Odd_Even_n	: boolean := false	-- false => Even Parity, true => Odd Parity
+	);
+	port(
+		TXD				: out std_logic
+	);
+end AsyncStim;
+
+architecture behaviour of AsyncStim is
+
+	signal	TX_ShiftReg		: std_logic_vector(Bits - 1 downto 0);
+	signal	TX_Bit_Cnt		: integer range 0 to 15 := 0;
+	signal	ParTmp			: boolean;
+
+begin
+
+	process
+		type ChFile is file of character;
+		file InFile				: ChFile open read_mode is FileName;
+		variable Inited			: boolean := false;
+		variable CharTmp		: character;
+		variable IntTmp			: integer;
+	begin
+		if not Inited then
+			Inited := true;
+			TXD <= '1';
+		end if;
+		wait for 1000000000 ns / Baud;
+		TX_Bit_Cnt <= TX_Bit_Cnt + 1;
+		case TX_Bit_Cnt is
+		when 0 =>
+			TXD <= '1';
+			wait for InterCharDelay;
+		when 1 => -- Start bit
+			read(InFile, CharTmp);
+			IntTmp := character'pos(CharTmp);
+			TX_ShiftReg(Bits - 1 downto 0) <= std_logic_vector(to_unsigned(IntTmp, Bits));
+			TXD <= '0';
+			ParTmp <= P_Odd_Even_n;
+		when others =>
+			TXD <= TX_ShiftReg(0);
+			ParTmp <= ParTmp xor (TX_ShiftReg(0) = '1');
+			TX_ShiftReg(Bits - 2 downto 0) <= TX_ShiftReg(Bits - 1 downto 1);
+			if (TX_Bit_Cnt = Bits + 1 and not Parity) or
+				(TX_Bit_Cnt = Bits + 2 and Parity) then -- Stop bit
+				TX_Bit_Cnt <= 0;
+			end if;
+			if Parity and TX_Bit_Cnt = Bits + 2 then
+				if ParTmp then
+					TXD <= '1';
+				else
+					TXD <= '0';
+				end if;
+			end if;
+		end case;
+	end process;
+
+end;
diff --git a/bench/vhdl/BinaryLog.vhd b/bench/vhdl/BinaryLog.vhd
new file mode 100644
index 0000000..10c2670
--- /dev/null
+++ b/bench/vhdl/BinaryLog.vhd
@@ -0,0 +1,93 @@
+--
+-- Output port with binary file log
+--
+-- Version : 0146
+--
+-- Copyright (c) 2001 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--	http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity BinaryLog is
+	generic(
+		FileName		: string;
+		Bytes			: integer := 1;		-- Number of bytes per word
+		LittleEndian	: boolean := true	-- Byte order
+	);
+	port(
+		Clk				: in std_logic;
+		En				: in std_logic;
+		Data			: in std_logic_vector(Bytes * 8 - 1 downto 0)
+	);
+end BinaryLog;
+
+architecture behaviour of BinaryLog is
+
+	function to_char(
+		constant Byte : std_logic_vector(7 downto 0)
+	) return character is
+	begin
+		return character'val(to_integer(unsigned(Byte)));
+	end function;
+
+begin
+
+	process (clk)
+		type ChFile is file of character;
+		file OutFile : ChFile open write_mode is FileName;
+	begin
+		if Clk'event and Clk = '1' and En = '1' and now > 0 ns then
+			if LittleEndian then
+				for i in integer range 0 to Bytes - 1 loop
+					write(OutFile, to_char(Data(i * 8 + 7 downto i * 8)));
+				end loop;
+			else
+				for i in integer range Bytes - 1 downto 0 loop
+					write(OutFile, to_char(Data(i * 8 + 7 downto i * 8)));
+				end loop;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/bench/vhdl/BinaryStim.vhd b/bench/vhdl/BinaryStim.vhd
new file mode 100644
index 0000000..626876a
--- /dev/null
+++ b/bench/vhdl/BinaryStim.vhd
@@ -0,0 +1,95 @@
+--
+-- Input port with stimuli from binary file
+--
+-- Version : 0146
+--
+-- Copyright (c) 2001 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--	http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity BinaryStim is
+	generic(
+		FileName		: string;
+		Bytes			: integer := 1;		-- Number of bytes per word
+		LittleEndian	: boolean := true	-- Byte order
+	);
+	port(
+		Rd				: in std_logic;
+		Data			: out std_logic_vector(Bytes * 8 - 1 downto 0)
+	);
+end BinaryStim;
+
+architecture behaviour of BinaryStim is
+
+begin
+
+	process (Rd)
+		type ChFile is file of character;
+		file InFile				: ChFile open read_mode is FileName;
+		variable Inited			: boolean := false;
+		variable CharTmp		: character;
+		variable IntTmp			: integer;
+	begin
+		if not Inited then
+			Inited := true;
+		end if;
+		if Rd'event and Rd = '1' and now > 0 ns then
+			if LittleEndian then
+				for i in integer range 0 to Bytes - 1 loop
+					read(InFile, CharTmp);
+					IntTmp := character'pos(CharTmp);
+					Data(i * 8 + 7 downto i * 8) <= std_logic_vector(to_unsigned(IntTmp, 8));
+				end loop;
+			else
+				for i in integer range Bytes - 1 downto 0 loop
+					read(InFile, CharTmp);
+					IntTmp := character'pos(CharTmp);
+					Data(i * 8 + 7 downto i * 8) <= std_logic_vector(to_unsigned(IntTmp, 8));
+				end loop;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/bench/vhdl/I2SLog.vhd b/bench/vhdl/I2SLog.vhd
new file mode 100644
index 0000000..ed4dc6f
--- /dev/null
+++ b/bench/vhdl/I2SLog.vhd
@@ -0,0 +1,106 @@
+--
+-- I2S port with binary file log
+--
+-- Version : 0146
+--
+-- Copyright (c) 2001 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--	http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity I2SLog is
+	generic(
+		FileName		: string;
+		Bytes			: integer := 2;		-- Number of bytes per word
+		LittleEndian	: boolean := true	-- Byte order
+	);
+	port(
+		BClk			: in std_logic;
+		FSync			: in std_logic;
+		SData			: in std_logic
+	);
+end I2SLog;
+
+architecture behaviour of I2SLog is
+
+	function to_char(
+		constant Byte : std_logic_vector(7 downto 0)
+	) return character is
+	begin
+		return character'val(to_integer(unsigned(Byte)));
+	end function;
+
+begin
+	process (BClk)
+		type ChFile is file of character;
+		file OutFile	: ChFile open write_mode is FileName;
+		variable Data	: std_logic_vector(Bytes * 8 - 1 downto 0);
+		variable BPhase	: integer := 64;
+		variable OldFS	: std_logic;
+	begin
+		if BClk'event and BClk = '1' then
+			if BPhase mod 32 = Bytes * 8 then
+				if LittleEndian then
+					for i in integer range 0 to Bytes - 1 loop
+						write(OutFile, to_char(Data(i * 8 + 7 downto i * 8)));
+					end loop;
+				else
+					for i in integer range Bytes - 1 downto 0 loop
+						write(OutFile, to_char(Data(i * 8 + 7 downto i * 8)));
+					end loop;
+				end if;
+			end if;
+
+			if OldFS = '1' and FSync = '0' then
+				BPhase := 0;
+			else
+				BPhase := BPhase + 1;
+			end if;
+			OldFS := FSync;
+
+			Data(Bytes * 8 - 1 downto 1) := Data(Bytes * 8 - 2 downto 0);
+			Data(0) := SData;
+		end if;
+	end process;
+end;
diff --git a/bench/vhdl/I2SStim.vhd b/bench/vhdl/I2SStim.vhd
new file mode 100644
index 0000000..d052414
--- /dev/null
+++ b/bench/vhdl/I2SStim.vhd
@@ -0,0 +1,117 @@
+--
+-- I2S from binary file
+--
+-- Version : 0146
+--
+-- Copyright (c) 2001 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--	http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity I2SStim is
+	generic(
+		FileName		: string;
+		Bytes			: integer := 2;		-- Number of bytes per word (1 to 4)
+		LittleEndian	: boolean := true	-- Byte order
+	);
+	port(
+		BClk			: in std_logic;
+		FSync			: in std_logic;
+		SData			: out std_logic
+	);
+end I2SStim;
+
+architecture behaviour of I2SStim is
+
+begin
+	process (BClk)
+		type ChFile is file of character;
+		file InFile				: ChFile open read_mode is FileName;
+		variable Inited			: boolean := false;
+		variable CharTmp		: character;
+		variable IntTmp			: integer;
+		variable Data			: std_logic_vector(Bytes * 8 - 1 downto 0);
+		variable BPhase			: integer;
+		variable OldFS			: std_logic;
+	begin
+		if not Inited then
+			Inited := true;
+			BPhase := 64;
+			Data := (others => '0');
+			SData <= '0';
+		end if;
+		if BClk'event and BClk = '0' then
+			if BPhase = 0 or BPhase = 32 then
+				if LittleEndian then
+					for i in integer range 0 to Bytes - 1 loop
+						read(InFile, CharTmp);
+						IntTmp := character'pos(CharTmp);
+						Data(i * 8 + 7 downto i * 8) := std_logic_vector(to_unsigned(IntTmp, 8));
+					end loop;
+				else
+					for i in integer range Bytes - 1 downto 0 loop
+						read(InFile, CharTmp);
+						IntTmp := character'pos(CharTmp);
+						Data(i * 8 + 7 downto i * 8) := std_logic_vector(to_unsigned(IntTmp, 8));
+					end loop;
+				end if;
+			end if;
+
+			if BPhase mod 32 < Bytes * 8 then
+				SData <= Data(Bytes * 8 - 1);
+				Data(Bytes * 8 - 1 downto 1) := Data(Bytes * 8 - 2 downto 0);
+			else
+				SData <= '0';
+			end if;
+		end if;
+		if BClk'event and BClk = '1' then
+			if OldFS = '1' and FSync = '0' then
+				BPhase := 0;
+			else
+				BPhase := BPhase + 1;
+			end if;
+			OldFS := FSync;
+		end if;
+	end process;
+end;
diff --git a/bench/vhdl/IntegerLog.vhd b/bench/vhdl/IntegerLog.vhd
new file mode 100644
index 0000000..da77ce6
--- /dev/null
+++ b/bench/vhdl/IntegerLog.vhd
@@ -0,0 +1 @@
+--
+-- File I/O test-bench utilities
+--
+-- Version : 0146
+--
+-- Copyright (c) 2001 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--	http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+library IEEE;
+use IEEE.std_logic_1164.all;
+use std.textio.all;
+entity IntegerLog is
+	generic(
+		FileName		: string
+	);
+	port(
+		Clk				: in std_logic;
+		En				: in std_logic;
+		Data			: in integer
+	);
+end IntegerLog;
+architecture behaviour of IntegerLog is
+begin
+	process (Clk)
+		file OutFile : text open write_mode is FileName;
+		variable l : line;
+	begin
+		if Clk'event and Clk = '1' and En = '1' and now > 0 ns then
+			write(l, Data);
+			writeline(OutFile, l);
+		end if;
+	end process;
+end;
+\ No newline at end of file
diff --git a/bench/vhdl/StimLog.vhd b/bench/vhdl/StimLog.vhd
new file mode 100644
index 0000000..662f9fd
--- /dev/null
+++ b/bench/vhdl/StimLog.vhd
@@ -0,0 +1,142 @@
+--
+-- File I/O test-bench utilities
+--
+-- Version : 0146
+--
+-- Copyright (c) 2001 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--	http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package StimLog is
+
+	component AsyncStim
+	generic(
+		FileName		: string;
+		Baud			: integer;
+		InterCharDelay	: time := 0 ns;
+		Bits			: integer := 8;		-- Data bits
+		Parity			: boolean := false;	-- Enable Parity
+		P_Odd_Even_n	: boolean := false	-- false => Even Parity, true => Odd Parity
+	);
+	port(
+		TXD				: out std_logic
+	);
+	end component;
+
+	component AsyncLog
+	generic(
+		FileName		: string;
+		Baud			: integer;
+		Bits			: integer := 8;		-- Data bits
+		Parity			: boolean := false;	-- Enable Parity
+		P_Odd_Even_n	: boolean := false	-- false => Even Parity, true => Odd Parity
+	);
+	port(
+		RXD				: in std_logic
+	);
+	end component;
+
+	component BinaryStim
+	generic(
+		FileName		: string;
+		Bytes			: integer := 1;		-- Number of bytes per word
+		LittleEndian	: boolean := true	-- Byte order
+	);
+	port(
+		Rd				: in std_logic;
+		Data			: out std_logic_vector(Bytes * 8 - 1 downto 0)
+	);
+	end component;
+
+	component BinaryLog
+	generic(
+		FileName		: string;
+		Bytes			: integer := 1;		-- Number of bytes per word
+		LittleEndian	: boolean := true	-- Byte order
+	);
+	port(
+		Clk				: in std_logic;
+		En				: in std_logic;
+		Data			: in std_logic_vector(Bytes * 8 - 1 downto 0)
+	);
+	end component;
+
+	component I2SStim is
+	generic(
+		FileName		: string;
+		Bytes			: integer := 2;		-- Number of bytes per word (1 to 4)
+		LittleEndian	: boolean := true	-- Byte order
+	);
+	port(
+		BClk			: in std_logic;
+		FSync			: in std_logic;
+		SData			: out std_logic
+	);
+	end component;
+
+	component I2SLog is
+	generic(
+		FileName		: string;
+		Bytes			: integer := 2;		-- Number of bytes per word
+		LittleEndian	: boolean := true	-- Byte order
+	);
+	port(
+		BClk			: in std_logic;
+		FSync			: in std_logic;
+		SData			: in std_logic
+	);
+	end component;
+
+	component IntegerLog is
+	generic(
+		FileName		: string
+	);
+	port(
+		Clk				: in std_logic;
+		En				: in std_logic;
+		Data			: in integer
+	);
+	end component;
+
+end;
diff --git a/bench/vhdl/TestBench32.vhd b/bench/vhdl/TestBench32.vhd
new file mode 100644
index 0000000..af4189b
--- /dev/null
+++ b/bench/vhdl/TestBench32.vhd
@@ -0,0 +1,116 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use work.StimLog.all;
+
+entity TestBench32 is
+end TestBench32;
+
+architecture behaviour of TestBench32 is
+
+	signal CLK_I		: std_logic := '0';
+	signal RST_I		: std_logic := '1';
+	signal ACK_I		: std_logic;
+	signal TAG0_O		: std_logic;
+	signal CYC_O		: std_logic;
+	signal STB_O		: std_logic;
+	signal WE_O			: std_logic;
+	signal ADR_O		: std_logic_vector(15 downto 0);
+	signal ADR_O_r		: std_logic_vector(15 downto 0);
+	signal DAT_I		: std_logic_vector(7 downto 0);
+	signal DAT_O		: std_logic_vector(7 downto 0);
+	signal ROM_D		: std_logic_vector(7 downto 0);
+	signal RAM_D		: std_logic_vector(7 downto 0);
+	signal CS_n			: std_logic;
+	signal WE_n			: std_logic;
+	signal RXD			: std_logic;
+	signal RXD_IsOut	: std_logic;
+	signal RXD_Out		: std_logic;
+	signal TXD			: std_logic;
+	signal INT0			: std_logic := '0';
+	signal P0			: std_logic_vector(7 downto 0);
+	signal P1			: std_logic_vector(7 downto 0);
+	signal P2			: std_logic_vector(7 downto 0);
+	signal P3			: std_logic_vector(7 downto 0);
+	signal p3_out	: std_logic_vector(7 downto 0);
+
+begin
+
+	u0 : entity work.T8032
+		port map(
+			CLK_I => CLK_I,
+			RST_I => RST_I,
+			ACK_I => ACK_I,
+			TAG0_O => TAG0_O,
+			CYC_O => CYC_O,
+			STB_O => STB_O,
+			WE_O => WE_O,
+			ADR_O => ADR_O,
+			DAT_I => DAT_I,
+			DAT_O => DAT_O,
+			P0_in => P0,
+			P1_in => P1,
+			P2_in => P2,
+			P3_in => P3,
+			P0_out => P0,
+      P1_out => P1,
+      P2_out => P2,
+      P3_out => P3_out,
+			INT0 => INT0,
+			INT1 => '1',
+			T0 => '1',
+			T1 => '1',
+			T2 => '1',
+			T2EX => '1',
+			RXD => RXD,
+			RXD_IsO => RXD_IsOut,
+			RXD_O => RXD_Out,
+			TXD => TXD);
+
+	rom : entity work.ROM52
+		port map(
+			Clk	=> CLK_I,
+			A => ADR_O(12 downto 0),
+			D => ROM_D);
+
+	WE_n <= WE_O nand ACK_I;
+	CS_n <= '0' when ADR_O(15 downto 11) = "00000" and TAG0_O = '1' else '1';
+
+	ram : entity work.SSRAM
+		generic map(
+			AddrWidth => 11)
+		port map(
+			Clk => CLK_I,
+			CE_n => '0',
+			WE_n => WE_n,
+			A => ADR_O(10 downto 0),
+			DIn => DAT_O,
+			DOut => RAM_D);
+
+	DAT_I <= ROM_D when TAG0_O = '0' else RAM_D when ADR_O(15 downto 11) = "00000" else "11111111";
+	ACK_I <= '1' when ADR_O_r = ADR_O else '0';
+
+	P3(0) <= RXD;
+  P3(7 downto 1) <= P3_out(7 downto 1);
+  
+	process (CLK_I)
+	begin
+		if CLK_I'event and CLK_I = '1' then
+			ADR_O_r <= ADR_O;
+		end if;
+	end process;
+
+	as : AsyncStim
+		generic map(FileName => "BASIC.txt", InterCharDelay => 5000 us, Baud => 57600, Bits => 8)
+		port map(RXD);
+
+
+	al : AsyncLog
+		generic map(FileName => "RX_Log.txt", Baud => 57600, Bits => 8)
+		port map(TXD);
+
+	CLK_I <= not CLK_I after 45 ns;
+	RST_I <= '0' after 200 ns;
+
+	INT0 <= not INT0 after 100 us;
+
+end;
diff --git a/bench/vhdl/TestBench52.vhd b/bench/vhdl/TestBench52.vhd
new file mode 100644
index 0000000..faeb051
--- /dev/null
+++ b/bench/vhdl/TestBench52.vhd
@@ -0,0 +1,79 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use work.StimLog.all;
+
+entity TestBench52 is
+end TestBench52;
+
+architecture behaviour of TestBench52 is
+
+	signal Clk			: std_logic := '0';
+	signal Rst_n		: std_logic := '0';
+	signal RXD			: std_logic;
+	signal RXD_IsOut	: std_logic;
+	signal RXD_Out		: std_logic;
+	signal TXD			: std_logic;
+	signal INT0			: std_logic := '0';
+	signal P0			: std_logic_vector(7 downto 0);
+	signal P1			: std_logic_vector(7 downto 0);
+	signal P2			: std_logic_vector(7 downto 0);
+	signal P3			: std_logic_vector(7 downto 0);
+	signal p3_out	: std_logic_vector(7 downto 0);
+  signal XRAM_WE_s   : std_logic;
+  signal XRAM_STB_s  : std_logic;
+  signal XRAM_CYC_s  : std_logic;
+  signal XRAM_ACK_s  : std_logic;
+  signal XRAM_DATI_s : std_logic_vector(7 downto 0);
+  signal XRAM_ADR_s  : std_logic_vector(15 downto 0);
+  signal XRAM_DATO_s : std_logic_vector(7 downto 0);
+
+begin
+
+	u0 : entity work.T8052
+		port map(
+			Clk => Clk,
+			Rst_n => Rst_n,
+			P0_in => P0,
+			P1_in => P1,
+			P2_in => P2,
+			P3_in => P3,
+			P0_out => P0,
+      P1_out => P1,
+      P2_out => P2,
+      P3_out => P3_out,
+			INT0 => INT0,
+			INT1 => '1',
+			T0 => '1',
+			T1 => '1',
+			T2 => '1',
+			T2EX => '1',
+			RXD => RXD,
+			RXD_IsO => RXD_IsOut,
+			RXD_O => RXD_Out,
+			TXD => TXD,
+			XRAM_WE_O  => XRAM_WE_s, 
+      XRAM_STB_O => XRAM_STB_s,
+      XRAM_CYC_O => XRAM_CYC_s,
+      XRAM_ACK_I => XRAM_ACK_s,
+      XRAM_DAT_O => XRAM_DATO_s,
+      XRAM_ADR_O => XRAM_ADR_s,
+      XRAM_DAT_I => XRAM_DATI_s
+			);
+      
+	P3(0) <= RXD;
+	P3(7 downto 1) <= P3_out(7 downto 1);
+	XRAM_DATI_s    <= (others => '1');
+	XRAM_ACK_s     <= XRAM_STB_s;
+
+	as : AsyncStim generic map(FileName => "BASIC.txt", InterCharDelay => 5000 us, Baud => 57600, Bits => 8)
+				port map(RXD);
+
+	al : AsyncLog generic map(FileName => "RX_Log.txt", Baud => 57600, Bits => 8)
+				port map(TXD);
+
+	Clk <= not Clk after 45 ns;
+	Rst_n <= '1' after 200 ns;
+
+	INT0 <= not INT0 after 100 us;
+
+end;