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authorOxore <oxore@protonmail.com>2019-07-14 19:49:23 +0300
committerOxore <oxore@protonmail.com>2019-07-14 19:49:23 +0300
commit32ebeb3baf707df400f311d7489e424e5492ecf2 (patch)
tree69e16b525113f4e7d6dc108f4af4f403dfa79eca
parent24e3ef936efd5b9239de76088efa02d06537ceb6 (diff)
Implement ram and instructions
-rw-r--r--src/core.rs41
-rw-r--r--src/main.rs3
2 files changed, 41 insertions, 3 deletions
diff --git a/src/core.rs b/src/core.rs
index 0062e1c..6c6eefd 100644
--- a/src/core.rs
+++ b/src/core.rs
@@ -1,14 +1,51 @@
+use std::fmt;
+
+#[derive(Debug)]
+pub enum Op {
+ Nop,
+ Illegal,
+}
+
+impl fmt::Display for Op {
+ fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+ write!(f, "{:?}", self)
+ }
+}
+
pub struct Core {
pc: u16,
+ ram: [u8; u16::max_value() as usize + 1],
}
impl Core {
pub fn new() -> Self {
- Core { pc: 0 }
+ Core { pc: 0, ram: [0; u16::max_value() as usize + 1] }
}
pub fn step(&mut self) -> u16 {
- self.pc += 1;
+ self.pc += self.ram[self.pc as usize].instruction_size();
self.pc
}
+
+ pub fn op(&self) -> Op {
+ self.ram[self.pc as usize].op()
+ }
+}
+
+pub trait Isa {
+ fn op(&self) -> Op;
+ fn instruction_size(&self) -> u16;
+}
+
+impl Isa for u8 {
+ fn op(&self) -> Op {
+ match *self {
+ 0 => Op::Nop,
+ _ => Op::Illegal
+ }
+ }
+
+ fn instruction_size(&self) -> u16 {
+ 1
+ }
}
diff --git a/src/main.rs b/src/main.rs
index f5af35c..974ff5c 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -10,7 +10,8 @@ use self::core::Core;
fn core_worker(mut core: Core, should_stop: &Mutex<bool>, cvar: &Condvar) {
loop {
while false == *should_stop.lock().unwrap() {
- println!("step {}", core.step());
+ core.step();
+ println!("{}", core.op());
sleep(time::Duration::from_millis(1000));
}