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#include "ltimers_config.h"
#include "stm32f0xx_conf.h"
// ----------------------------------------------------------------------------
// Èíèöèàëèçàöèÿ àïïàðàòíîãî òàéìåðà äëÿ ãåíåðèðîâàíèÿ ïðåðûâàíèé êàæäóþ 1ìñ
// ----------------------------------------------------------------------------
void LTimersConfig ( void )
{
// NVIC_InitTypeDef NVIC_InitStructure;
// TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
//
// /* TIM6 clock enable */
// RCC_APB1PeriphClockCmd ( RCC_APB1Periph_TIM6 , ENABLE );
//
// /* Enable the TIM6 global Interrupt */
// NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
// NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
// NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
// NVIC_InitStructure.NVIC_IRQChannel = TIM6_IRQn;
// NVIC_Init ( &NVIC_InitStructure );
//
// /* Configure TIM6 to generate interrupt each 1ms */
// TIM_TimeBaseStructure.TIM_Period = 1000;
// TIM_TimeBaseStructure.TIM_Prescaler = (SystemCoreClock/1000000)-1;
// TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1;
// TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
// TIM_TimeBaseInit ( TIM6, &TIM_TimeBaseStructure );
//
// /* TIM6 IT enable */
// TIM_ITConfig ( TIM6, TIM_IT_Update , ENABLE );
//
// /* TIM6 enable counter */
// TIM_Cmd ( TIM6, ENABLE );
NVIC_InitTypeDef NVIC_InitStructure;
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
/* LTIMER_TIMx clock enable */
LTIMER_RCC_APBxPeriphClockCmd ( LTIMER_TIM_RCC, ENABLE );
/* Enable the LTIMER_TIMx gloabal Interrupt */
NVIC_InitStructure.NVIC_IRQChannel = LTIMER_TIM_IRQx;
NVIC_InitStructure.NVIC_IRQChannelPriority = 1;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init ( &NVIC_InitStructure );
/* -----------------------------------------------------------------------
In this example TIM7 counter clock (TIM7CLK) is set to APB1 clock (PCLK1), since
APB1 prescaler is set to 1 and TIM7 prescaler is set to 0.
In this example TIM7 input clock (TIM7CLK) is set to APB1 clock (PCLK1),
since APB1 prescaler is set to 1.
TIM7CLK = PCLK1 = HCLK = SystemCoreClock
With Prescaler set to 479 and Period to 24999, the TIM7 counter is updated each 250 ms
(i.e. and interrupt is generated each 250 ms)
TIM7 counter clock = TIM7CLK /((Prescaler + 1)*(Period + 1))
= 48 MHz / ((25000)*(480))
= 4 Hz
==> TIM7 counter period = 250 ms
Note:
SystemCoreClock variable holds HCLK frequency and is defined in system_stm32f0xx.c file.
Each time the core clock (HCLK) changes, user had to call SystemCoreClockUpdate()
function to update SystemCoreClock variable value. Otherwise, any configuration
based on this variable will be incorrect.
----------------------------------------------------------------------- */
/* Time base configuration */
TIM_TimeBaseStructure.TIM_Period = 1000; //24999;
TIM_TimeBaseStructure.TIM_Prescaler = (SystemCoreClock/1000000)-1; //479;
TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1;
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
TIM_TimeBaseInit ( LTIMER_TIMx, &TIM_TimeBaseStructure );
/* LTIMER_TIMx Interrupts enable */
TIM_ITConfig ( LTIMER_TIMx, TIM_IT_Update, ENABLE );
/* LTIMER_TIMx enable counter */
TIM_Cmd ( LTIMER_TIMx, ENABLE );
}
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