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authorOxore <oxore@protonmail.com>2020-03-04 03:17:25 +0300
committerOxore <oxore@protonmail.com>2020-03-04 03:19:16 +0300
commit7d4dfd8af842796c4eb8a88df0cc5ab30f99232d (patch)
tree826f7b9453aa30ab18de73f97b18a6bb83b70734 /Readme.md
parent0a6fad82f83d7a79aa7eadf73a21e6e80c8e810d (diff)
Rename Core to Cpu8051 and Ram to ProgramMemory, etc.
Adjust Readme.md
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- At least one I/O Port (P0)
- Timer (with interrupts)
- Serial UART (with interrupts)
-- Cycle accurate emulation of program execution with synchronization of all the
+- Cycle accurate emulation of program execution and synchronization with all
peripherals.
-- Can bind execution speed to real host machine time with speed multiplier (e.g.
+- Locking execution speed to real host machine time with speed multiplier (e.g.
1 instruction per second, 1000 cycles per second).
- Every peripheral produces event with information of it's state if it changes.
CPU produces events on each step while in single step mode or when pause